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/linux/arch/mips/kernel/
H A Dirq-gt641xx.c22 u32 cause; in ack_gt641xx_irq() local
25 cause = GT_READ(GT_INTRCAUSE_OFS); in ack_gt641xx_irq()
26 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); in ack_gt641xx_irq()
27 GT_WRITE(GT_INTRCAUSE_OFS, cause); in ack_gt641xx_irq()
46 u32 cause, mask; in mask_ack_gt641xx_irq() local
53 cause = GT_READ(GT_INTRCAUSE_OFS); in mask_ack_gt641xx_irq()
54 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); in mask_ack_gt641xx_irq()
55 GT_WRITE(GT_INTRCAUSE_OFS, cause); in mask_ack_gt641xx_irq()
81 u32 cause, mask; in gt641xx_irq_dispatch() local
84 cause = GT_READ(GT_INTRCAUSE_OFS); in gt641xx_irq_dispatch()
[all …]
H A Dmips-cm.c375 int ocause, cause; in mips_cm_error_report() local
387 cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error); in mips_cm_error_report()
390 if (!cause) in mips_cm_error_report()
393 if (cause < 16) { in mips_cm_error_report()
404 } else if (cause < 24) { in mips_cm_error_report()
439 cm2_causes[cause], buf); in mips_cm_error_report()
446 cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error); in mips_cm_error_report()
449 if (!cause) in mips_cm_error_report()
452 /* Used by cause == {1,2,3} */ in mips_cm_error_report()
462 if (cause == 1 || cause == 3) { /* Tag ECC */ in mips_cm_error_report()
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
13 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
91 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
96 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
120 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
13 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
91 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
96 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
120 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
13 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
91 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
96 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
120 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
[all …]
/linux/arch/mips/bcm47xx/
H A Dirq.c36 u32 cause; in plat_irq_dispatch() local
38 cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; in plat_irq_dispatch()
40 clear_c0_status(cause); in plat_irq_dispatch()
42 if (cause & CAUSEF_IP7) in plat_irq_dispatch()
44 if (cause & CAUSEF_IP2) in plat_irq_dispatch()
46 if (cause & CAUSEF_IP3) in plat_irq_dispatch()
48 if (cause & CAUSEF_IP4) in plat_irq_dispatch()
50 if (cause & CAUSEF_IP5) in plat_irq_dispatch()
52 if (cause & CAUSEF_IP6) in plat_irq_dispatch()
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dvirtual-memory.json15 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
20 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
47 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
56 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
60 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
65 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
109 "BriefDescription": "Misses at all ITLB levels that cause page walks",
113 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
118 …n": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
127 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
11 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
15 …d operations that miss the first DTLB level but hit the second and do not cause any page walks. Th…
20 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
37 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
45 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
53 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
85 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
93 …": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
101 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
11 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
15 …d operations that miss the first DTLB level but hit the second and do not cause any page walks. Th…
20 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
37 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
45 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
53 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
85 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
93 …": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
101 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dvirtual-memory.json31 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
36 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
63 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
72 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
76 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
81 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
125 "BriefDescription": "Misses at all ITLB levels that cause page walks",
129 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
134 …n": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
143 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
[all …]
/linux/security/integrity/ima/
H A Dima_appraise.c280 enum integrity_status *status, const char **cause) in xattr_verify() argument
296 *cause = "verity-signature-required"; in xattr_verify()
298 *cause = "IMA-signature-required"; in xattr_verify()
318 *cause = "invalid-hash"; in xattr_verify()
329 *cause = "verity-signature-required"; in xattr_verify()
336 *cause = "invalid-signature-version"; in xattr_verify()
357 *cause = "invalid-signature"; in xattr_verify()
368 *cause = "IMA-signature-required"; in xattr_verify()
376 *cause = "invalid-signature-version"; in xattr_verify()
386 *cause = "sigv3-hashing-error"; in xattr_verify()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dsubr.c191 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler() local
194 if (cause & (1 << p)) { in fpga_phy_intr_handler()
201 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler()
210 u32 cause = readl(adapter->regs + A_PL_CAUSE); in fpga_slow_intr() local
213 cause &= ~F_PL_INTR_SGE_DATA; in fpga_slow_intr()
214 if (cause & F_PL_INTR_SGE_ERR) { in fpga_slow_intr()
219 if (cause & FPGA_PCIX_INTERRUPT_GMAC) in fpga_slow_intr()
222 if (cause & FPGA_PCIX_INTERRUPT_TP) { in fpga_slow_intr()
232 if (cause & FPGA_PCIX_INTERRUPT_PCIX) { in fpga_slow_intr()
238 if (cause) in fpga_slow_intr()
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
21 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
34 …ons from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
43 …ons from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
92 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
110 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
114 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
123 …ons from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
132 …ons from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dvirtual-memory.json3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
21 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
34 …ons from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
43 …ons from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
92 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
110 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
114 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
123 …ons from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
132 …ons from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
[all …]
/linux/arch/mips/kvm/
H A Dvz.c258 u32 cause) in kvm_vz_irq_deliver_cb() argument
287 u32 cause) in kvm_vz_irq_clear_cb() argument
295 * Explicitly clear irq associated with Cause.IP[IPTI] in kvm_vz_irq_clear_cb()
360 * @cause: CP0_Cause register to restore.
366 u32 cause) in _kvm_vz_restore_stimer() argument
375 write_gc0_cause(cause); in _kvm_vz_restore_stimer()
382 * @cause: CP0_Cause register to restore.
384 * Restore hard timer Guest.Count & Guest.Cause taking care to preserve the
388 u32 compare, u32 cause) in _kvm_vz_restore_htimer() argument
404 write_gc0_cause(cause); in _kvm_vz_restore_htimer()
[all …]
/linux/arch/nios2/kernel/
H A Dtraps.c94 * down the cause of the crash will be able to figure in show_stack()
122 asmlinkage void handle_unaligned_c(struct pt_regs *fp, int cause) in handle_unaligned_c() argument
126 cause >>= 2; in handle_unaligned_c()
136 pr_alert(" cause %d\n", cause); in handle_unaligned_c()
168 asmlinkage void unhandled_exception(struct pt_regs *regs, int cause) in unhandled_exception() argument
172 cause /= 4; in unhandled_exception()
175 cause, user_mode(regs) ? "user" : "kernel", addr); in unhandled_exception()
/linux/arch/mips/sgi-ip30/
H A Dip30-irq.c46 u64 pending, mask, cause, error_irqs, err_reg; in ip30_error_irq() local
52 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
66 * If we also have a cause value, then something happened, so loop in ip30_error_irq()
68 * and print the value of the HEART cause register. This is really in ip30_error_irq()
72 * Refer to heart.h for the HC_* macros to work out the cause in ip30_error_irq()
75 if (cause) { in ip30_error_irq()
76 pr_alert("IP30: CPU%d: HEART ATTACK! ISR = 0x%.16llx, IMR = 0x%.16llx, CAUSE = 0x%.16llx\n", in ip30_error_irq()
77 cpu, pending, mask, cause); in ip30_error_irq()
79 if (cause & HC_COR_MEM_ERR) { in ip30_error_irq()
/linux/security/integrity/
H A Dintegrity_audit.c30 const char *cause, int result, int audit_info) in integrity_audit_msg() argument
32 integrity_audit_message(audit_msgno, inode, fname, op, cause, in integrity_audit_msg()
38 const char *cause, int result, int audit_info, in integrity_audit_message() argument
56 audit_log_format(ab, " op=%s cause=%s comm=", op, cause); in integrity_audit_message()
/linux/arch/nios2/mm/
H A Dfault.c43 asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long cause, in do_page_fault() argument
53 cause >>= 2; in do_page_fault()
99 switch (cause) { in do_page_fault()
169 /* User mode accesses just cause a SIGSEGV */ in do_page_fault()
173 "cause %ld\n", current->comm, SIGSEGV, address, cause); in do_page_fault()
194 pr_alert("ea = %08lx, ra = %08lx, cause = %ld\n", regs->ea, regs->ra, in do_page_fault()
195 cause); in do_page_fault()
/linux/arch/mips/bcm63xx/
H A Dirq.c163 u32 cause; in plat_irq_dispatch() local
166 cause = read_c0_cause() & read_c0_status() & ST0_IM; in plat_irq_dispatch()
168 if (!cause) in plat_irq_dispatch()
171 if (cause & CAUSEF_IP7) in plat_irq_dispatch()
173 if (cause & CAUSEF_IP0) in plat_irq_dispatch()
175 if (cause & CAUSEF_IP1) in plat_irq_dispatch()
177 if (cause & CAUSEF_IP2) in plat_irq_dispatch()
180 if (cause & CAUSEF_IP3) in plat_irq_dispatch()
183 if (cause & CAUSEF_IP3) in plat_irq_dispatch()
185 if (cause & CAUSEF_IP4) in plat_irq_dispatch()
[all …]
/linux/Documentation/core-api/
H A Dunaligned-memory-access.rst15 unaligned accesses, why you need to write code that doesn't cause them,
73 platforms and will cause performance problems on others.
76 Code that does not cause unaligned access
95 not be unreasonable to expect that accessing field2 would cause an unaligned
111 will never cause an unaligned access, because all memory addresses are evenly
139 the memory access in a way that does not cause unaligned access. Of course,
140 the extra instructions obviously cause a loss in performance compared to the
149 that can cause an unaligned memory access. The following function taken
183 Here is another example of some code that could cause unaligned accesses::
192 This code will cause unaligned accesses every time the data parameter points
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-greatlakes.dts250 /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
251 "reset-cause-nic-secondary","","","",
265 /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
269 "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
270 "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
281 /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
/linux/tools/testing/selftests/kvm/x86_64/
H A Dsvm_nested_shutdown_test.c
/linux/include/trace/events/
H A Dfirewire.h836 #define show_cause(cause) \ argument
837 __print_symbolic(cause, \
845 …fw_iso_context *ctx, u16 timestamp, enum fw_iso_context_completions_cause cause, const u32 *header…
846 TP_ARGS(ctx, timestamp, cause, header, header_length),
851 __field(u8, cause)
858 __entry->cause = cause;
862 "context=0x%llx card_index=%u timestamp=0x%04x cause=%s header=%s",
866 show_cause(__entry->cause),
873 …fw_iso_context *ctx, u16 timestamp, enum fw_iso_context_completions_cause cause, const u32 *header…
874 TP_ARGS(ctx, timestamp, cause, header, header_length),
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dmc5.c370 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); in t3_mc5_intr_handler() local
372 if ((cause & F_PARITYERR) && mc5->parity_enabled) { in t3_mc5_intr_handler()
377 if (cause & F_REQQPARERR) { in t3_mc5_intr_handler()
382 if (cause & F_DISPQPARERR) { in t3_mc5_intr_handler()
387 if (cause & F_ACTRGNFULL) in t3_mc5_intr_handler()
389 if (cause & F_NFASRCHFAIL) in t3_mc5_intr_handler()
391 if (cause & F_UNKNOWNCMD) in t3_mc5_intr_handler()
393 if (cause & F_DELACTEMPTY) in t3_mc5_intr_handler()
395 if (cause & MC5_INT_FATAL) in t3_mc5_intr_handler()
398 t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); in t3_mc5_intr_handler()

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