| /linux/drivers/media/platform/qcom/venus/ |
| H A D | hfi_platform_v4.c | 7 static const struct hfi_plat_caps caps[] = { variable
12 .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1},
13 .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1},
14 .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1},
15 .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1},
16 .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1},
17 .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1},
18 .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1},
19 .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1},
20 .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1},
[all …]
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| H A D | hfi_platform_v6.c | 7 static const struct hfi_plat_caps caps[] = { variable
12 .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 8192, 1},
13 .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 128, 8192, 1},
15 .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 64, 138240, 1},
16 .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 220000000, 1},
17 .caps[4] = {HFI_CAPABILITY_SCALE_X, 65536, 65536, 1},
18 .caps[5] = {HFI_CAPABILITY_SCALE_Y, 65536, 65536, 1},
19 .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 64, 7833600, 1},
20 .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 960, 1},
21 .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 0, 1, 1},
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| H A D | hfi_parser.c | 19 struct hfi_plat_caps *caps = core->caps, *cap; in init_codecs() local
26 cap = &caps[core->codecs_count++]; in init_codecs()
33 cap = &caps[core->codecs_count++]; in init_codecs()
40 static void for_each_codec(struct hfi_plat_caps *caps, unsigned int caps_num, in for_each_codec() argument
48 cap = &caps[i]; in for_each_codec()
80 for_each_codec(core->caps, ARRAY_SIZE(core->caps), in parse_alloc_mode()
111 for_each_codec(core->caps, ARRAY_SIZE(core->caps), codecs, domain, in parse_profile_level()
118 const struct hfi_capability *caps = data; in fill_caps() local
123 memcpy(&cap->caps[cap->num_caps], caps, num * sizeof(*caps)); in fill_caps()
130 struct hfi_capabilities *caps = data; in parse_caps() local
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| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 21 .caps = MDP_CAP_SMP |
41 .caps = MDP_PIPE_CAP_HFLIP |
50 .caps = MDP_PIPE_CAP_HFLIP |
58 .caps = MDP_PIPE_CAP_HFLIP |
67 .caps = MDP_LM_CAP_DISPLAY, },
69 .caps = MDP_LM_CAP_DISPLAY, },
71 .caps = MDP_LM_CAP_DISPLAY, },
73 .caps = MDP_LM_CAP_WB },
75 .caps = MDP_LM_CAP_WB },
110 .caps = MDP_CAP_SMP |
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| H A D | mdp5_pipe.c | 10 uint32_t caps, uint32_t blkcfg, in mdp5_pipe_assign() argument
44 /* skip if doesn't support some required caps: */ in mdp5_pipe_assign()
45 if (caps & ~cur->caps) in mdp5_pipe_assign()
52 if (cur->caps & MDP_PIPE_CAP_CURSOR && in mdp5_pipe_assign()
57 * fewest unneeded caps bits set: in mdp5_pipe_assign()
59 if (!(*hwpipe) || (hweight_long(cur->caps & ~caps) < in mdp5_pipe_assign()
60 hweight_long((*hwpipe)->caps & ~caps))) { in mdp5_pipe_assign()
70 if (r_cur->caps != cur->caps) in mdp5_pipe_assign()
109 DBG("%s: assign to plane %s for caps %x", in mdp5_pipe_assign()
110 (*hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
[all …]
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| /linux/drivers/infiniband/hw/hns/ |
| H A D | hns_roce_main.c | 71 if (port >= hr_dev->caps.num_ports) in hns_roce_add_gid()
85 if (port >= hr_dev->caps.num_ports) in hns_roce_del_gid()
138 for (port = 0; port < hr_dev->caps.num_ports; port++) { in hns_roce_netdev_event()
155 for (i = 0; i < hr_dev->caps.num_ports; i++) { in hns_roce_setup_mtu_mac()
173 props->fw_ver = hr_dev->caps.fw_ver; in hns_roce_query_device()
176 props->page_size_cap = hr_dev->caps.page_size_cap; in hns_roce_query_device()
180 props->max_qp = hr_dev->caps.num_qps; in hns_roce_query_device()
181 props->max_qp_wr = hr_dev->caps.max_wqes; in hns_roce_query_device()
184 props->max_send_sge = hr_dev->caps.max_sq_sg; in hns_roce_query_device()
185 props->max_recv_sge = hr_dev->caps.max_rq_sg; in hns_roce_query_device()
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| H A D | hns_roce_hw_v2.c | 1620 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); in hns_roce_query_fw_ver()
1660 if (port > hr_dev->caps.num_ports) in hns_roce_hw_v2_query_counter()
1724 struct hns_roce_caps *caps = &hr_dev->caps; in load_func_res_caps() local
1745 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; in load_func_res_caps()
1746 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; in load_func_res_caps()
1747 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; in load_func_res_caps()
1748 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; in load_func_res_caps()
1749 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; in load_func_res_caps()
1750 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; in load_func_res_caps()
1751 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; in load_func_res_caps()
[all …]
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| /linux/net/bluetooth/ |
| H A D | hci_codec.c | 12 void *caps, in hci_codec_list_add() argument
31 memcpy(entry->caps, caps, len); in hci_codec_list_add()
57 struct hci_codec_caps *caps; in hci_read_codec_capabilities() local
65 * then just add codec to the list without caps in hci_read_codec_capabilities()
100 caps = (void *)skb->data; in hci_read_codec_capabilities()
101 if (skb->len < sizeof(*caps)) in hci_read_codec_capabilities()
103 if (skb->len < caps->len) in hci_read_codec_capabilities()
105 len += sizeof(caps->len) + caps->len; in hci_read_codec_capabilities()
106 skb_pull(skb, sizeof(caps->len) + caps->len); in hci_read_codec_capabilities()
126 struct hci_op_read_local_codec_caps caps; in hci_read_supported_codecs() local
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| /linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | main.c | 295 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
307 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
308 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
316 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
317 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
330 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
331 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
343 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
359 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
395 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| H A D | dr_domain.c | 9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_7))
15 return dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX && in mlx5dr_domain_is_support_ptrn_arg()
16 dmn->info.caps.support_modify_argument; in mlx5dr_domain_is_support_ptrn_arg()
167 dmn->ste_ctx = mlx5dr_ste_get_ctx(dmn->info.caps.sw_format_ver); in dr_domain_init_resources()
230 struct mlx5dr_esw_caps *esw_caps = &dmn->info.caps.esw_caps; in dr_domain_fill_uplink_caps()
236 uplink_vport->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_fill_uplink_caps()
262 vport_caps->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_query_vport()
270 &dmn->info.caps.vports.esw_manager_caps); in dr_domain_query_esw_mgr()
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| H A D | dr_cmd.c | 69 struct mlx5dr_esw_caps *caps) in mlx5dr_cmd_query_esw_caps() argument
71 caps->drop_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
74 caps->drop_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
77 caps->uplink_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
80 caps->uplink_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
83 caps->sw_owner_v2 = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner_v2); in mlx5dr_cmd_query_esw_caps()
84 if (!caps->sw_owner_v2) in mlx5dr_cmd_query_esw_caps()
85 caps->sw_owner = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner); in mlx5dr_cmd_query_esw_caps()
112 struct mlx5dr_cmd_caps *caps) in mlx5dr_cmd_query_device() argument
117 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required); in mlx5dr_cmd_query_device()
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| H A D | dr_matcher.c | 109 dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_vxlan_gpe() argument
111 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_vxlan_gpe()
112 (caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED); in dr_matcher_supp_vxlan_gpe()
120 dr_matcher_supp_vxlan_gpe(&dmn->info.caps); in dr_mask_is_tnl_vxlan_gpe()
137 dr_matcher_supp_flex_parser_ok(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_flex_parser_ok() argument
139 return caps->flex_parser_ok_bits_supp; in dr_matcher_supp_flex_parser_ok()
145 return dr_matcher_supp_flex_parser_ok(&dmn->info.caps) && in dr_mask_is_tnl_geneve_tlv_opt_exist_set()
150 dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_tnl_geneve() argument
152 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_tnl_geneve()
153 (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED); in dr_matcher_supp_tnl_geneve()
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| /linux/drivers/net/ethernet/netronome/nfp/ |
| H A D | nfp_net_ctrl.c | 12 static void nfp_net_tlv_caps_reset(struct nfp_net_tlv_caps *caps) in nfp_net_tlv_caps_reset() argument
14 memset(caps, 0, sizeof(*caps)); in nfp_net_tlv_caps_reset()
15 caps->me_freq_mhz = 1200; in nfp_net_tlv_caps_reset()
16 caps->mbox_off = NFP_NET_CFG_MBOX_BASE; in nfp_net_tlv_caps_reset()
17 caps->mbox_len = NFP_NET_CFG_MBOX_VAL_MAX_SZ; in nfp_net_tlv_caps_reset()
21 nfp_net_tls_parse_crypto_ops(struct device *dev, struct nfp_net_tlv_caps *caps, in nfp_net_tls_parse_crypto_ops() argument
27 if (caps->tls_resync_ss && !rx_stream_scan) in nfp_net_tls_parse_crypto_ops()
37 caps->crypto_ops = readl(data); in nfp_net_tls_parse_crypto_ops()
38 caps->crypto_enable_off = data - ctrl_mem + 16; in nfp_net_tls_parse_crypto_ops()
39 caps->tls_resync_ss = rx_stream_scan; in nfp_net_tls_parse_crypto_ops()
[all …]
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| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | caps.c | 35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
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| /linux/drivers/gpu/drm/omapdrm/ |
| H A D | omap_overlay.c | 24 * Find a free overlay with the required caps and supported fourcc
28 u32 caps, u32 fourcc) in omap_plane_find_free_overlay() argument
33 DBG("caps: %x fourcc: %x", caps, fourcc); in omap_plane_find_free_overlay()
38 DBG("%d: id: %d cur->caps: %x", in omap_plane_find_free_overlay()
39 cur->idx, cur->id, cur->caps); in omap_plane_find_free_overlay()
45 /* skip if doesn't support some required caps: */ in omap_plane_find_free_overlay()
46 if (caps & ~cur->caps) in omap_plane_find_free_overlay()
62 * Assign a new overlay to a plane with the required caps and supported fourcc
69 u32 caps, u32 fourcc, struct omap_hw_overlay **overlay, in omap_overlay_assign() argument
77 ovl = omap_plane_find_free_overlay(s->dev, overlay_map, caps, fourcc); in omap_overlay_assign()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.c | 45 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
47 if (caps) { in dwb1_get_caps()
48 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb1_get_caps()
49 caps->hw_version = DCN_VERSION_1_0; in dwb1_get_caps()
50 caps->num_pipes = 2; in dwb1_get_caps()
51 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb1_get_caps()
52 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb1_get_caps()
53 caps->sw_version = dwb_ver_1_0; in dwb1_get_caps()
54 caps->caps.support_dwb = true; in dwb1_get_caps()
55 caps->caps.support_ogam = false; in dwb1_get_caps()
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| /linux/arch/powerpc/perf/ |
| H A D | hv-common.c | 8 unsigned long hv_perf_caps_get(struct hv_perf_caps *caps) in hv_perf_caps_get() argument
13 struct hv_gpci_system_performance_capabilities caps; in hv_perf_caps_get() member
31 pr_devel("capability_mask: 0x%x\n", arg.caps.capability_mask); in hv_perf_caps_get()
33 caps->version = arg.params.counter_info_version_out; in hv_perf_caps_get()
34 caps->collect_privileged = !!arg.caps.perf_collect_privileged; in hv_perf_caps_get()
35 caps->ga = !!(arg.caps.capability_mask & HV_GPCI_CM_GA); in hv_perf_caps_get()
36 caps->expanded = !!(arg.caps.capability_mask & HV_GPCI_CM_EXPANDED); in hv_perf_caps_get()
37 caps->lab = !!(arg.caps.capability_mask & HV_GPCI_CM_LAB); in hv_perf_caps_get()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| H A D | mlx5hws_context.c | 8 return IS_BIT_SET(ctx->caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_BY_STC); in mlx5hws_context_cap_dynamic_reparse()
39 max_log_sz = min(MLX5HWS_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max); in hws_context_pools_init()
40 pool_attr.alloc_log_sz = max(max_log_sz, ctx->caps->stc_alloc_log_gran); in hws_context_pools_init()
103 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_context_check_hws_supp() local
106 if (!caps->wqe_based_update) { in hws_context_check_hws_supp()
111 if (!caps->eswitch_manager) { in hws_context_check_hws_supp()
117 if ((!caps->nic_ft.reparse || in hws_context_check_hws_supp()
118 (!caps->fdb_ft.reparse && caps->eswitch_manager)) || in hws_context_check_hws_supp()
119 !IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) { in hws_context_check_hws_supp()
125 if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) { in hws_context_check_hws_supp()
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| /linux/tools/power/cpupower/utils/helpers/ |
| H A D | cpuid.c | 60 cpu_info->caps = 0; in get_cpu_info()
122 cpu_info->caps |= CPUPOWER_CAP_INV_TSC; in get_cpu_info()
126 cpu_info->caps |= CPUPOWER_CAP_APERF; in get_cpu_info()
133 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
136 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB_MSR; in get_cpu_info()
142 cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE; in get_cpu_info()
145 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATEDEF; in get_cpu_info()
151 cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; in get_cpu_info()
154 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; in get_cpu_info()
160 cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
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| /linux/arch/powerpc/platforms/pseries/ |
| H A D | vas-sysfs.c | 23 struct vas_cop_feat_caps *caps; member
32 static ssize_t update_total_credits_store(struct vas_cop_feat_caps *caps, in update_total_credits_store() argument
48 err = vas_reconfig_capabilties(caps->win_type, creds); in update_total_credits_store()
59 static ssize_t _name##_show(struct vas_cop_feat_caps *caps, char *buf) \
61 return sprintf(buf, "%d\n", atomic_read(&caps->_name)); \
125 struct vas_cop_feat_caps *caps; in vas_type_show() local
129 caps = centry->caps; in vas_type_show()
135 return entry->show(caps, buf); in vas_type_show()
142 struct vas_cop_feat_caps *caps; in vas_type_store() local
146 caps = centry->caps; in vas_type_store()
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| /linux/drivers/gpu/drm/stm/ |
| H A D | ltdc.c | 61 #define LAY_OFS (ldev->caps.layer_ofs)
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
93 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
94 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
95 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
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| /linux/drivers/pmdomain/mediatek/ |
| H A D | mt8188-pm-domains.h | 26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
88 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
98 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
120 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
128 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
136 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
153 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
170 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| H A D | dcn30_dwb.c | 46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
48 if (caps) { in dwb3_get_caps()
49 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb3_get_caps()
50 caps->hw_version = DCN_VERSION_3_0; in dwb3_get_caps()
51 caps->num_pipes = 2; in dwb3_get_caps()
52 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb3_get_caps()
53 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb3_get_caps()
54 caps->sw_version = dwb_ver_2_0; in dwb3_get_caps()
55 caps->caps.support_dwb = true; in dwb3_get_caps()
56 caps->caps.support_ogam = true; in dwb3_get_caps()
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_format_caps.c | 16 const struct komeda_format_caps *caps; in komeda_get_format_caps() local
22 caps = &table->format_caps[id]; in komeda_get_format_caps()
24 if (fourcc != caps->fourcc) in komeda_get_format_caps()
27 if ((modifier == 0ULL) && (caps->supported_afbc_layouts == 0)) in komeda_get_format_caps()
28 return caps; in komeda_get_format_caps()
30 if (has_bits(afbc_features, caps->supported_afbc_features) && in komeda_get_format_caps()
31 has_bit(afbc_layout, caps->supported_afbc_layouts)) in komeda_get_format_caps()
32 return caps; in komeda_get_format_caps()
99 const struct komeda_format_caps *caps; in komeda_format_mod_supported() local
101 caps = komeda_get_format_caps(table, fourcc, modifier); in komeda_format_mod_supported()
[all …]
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| /linux/drivers/crypto/stm32/ |
| H A D | stm32-cryp.c | 197 const struct stm32_cryp_caps *caps; member
307 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_busy()
313 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_CRYPEN, in stm32_cryp_enable()
314 cryp->regs + cryp->caps->cr); in stm32_cryp_enable()
321 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->cr, status, in stm32_cryp_wait_enable()
329 return readl_relaxed_poll_timeout_atomic(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_input()
337 return readl_relaxed_poll_timeout_atomic(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_output()
343 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_KEYRDEN, in stm32_cryp_key_read_enable()
344 cryp->regs + cryp->caps->cr); in stm32_cryp_key_read_enable()
349 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) & ~CR_KEYRDEN, in stm32_cryp_key_read_disable()
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