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/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,mipi-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
17 0 - MIPI CSIS 0,
18 1 - MIPI DSIM 0,
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dsamsung,exynos-sysreg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/samsung,exynos-sysreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC series System Registers (SYSREG)
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - items:
16 - enum:
17 - google,gs101-apm-sysreg
18 - google,gs101-hsi2-sysreg
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/linux/drivers/phy/samsung/
H A Dphy-exynos-mipi-video.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 EXYNOS_MIPI_PHY_ID_NONE = -1,
160 "samsung,pmu-syscon",
161 "samsung,disp-sysreg",
162 "samsung,cam0-sysreg",
163 "samsung,cam1-sysreg"
230 struct regmap *enable_map = state->regmaps[data->enable_map]; in __set_phy_state()
231 struct regmap *resetn_map = state->regmaps[data->resetn_map]; in __set_phy_state()
233 spin_lock(&state->slock); in __set_phy_state()
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/exynos3250.h>
17 #include "clk-cpu.h"
18 #include "clk-pll.h"
504 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
633 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
828 exynos3_core_down_clock(ctx->reg_base); in exynos3250_cmu_init()
830 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
940 CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
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H A Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
20 #include "clk-cpu.h"
21 #include "clk-exynos-arm64.h"
22 #include "clk-pll.h"
792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
794 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
795 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
796 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
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