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Searched full:cacheability (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/arm64/iommu/
H A Dsmmureg.h133 #define CR1_TABLE_OC_S 8 /* Table access Outer Cacheability. */
138 #define CR1_TABLE_IC_S 6 /* Table access Inner Cacheability. */
148 #define CR1_QUEUE_OC_S 2 /* Queue access Outer Cacheability. */
153 #define CR1_QUEUE_IC_S 0 /* Queue access Inner Cacheability. */
415 #define CD0_IR0_S 8 /* Inner region Cacheability for TT0 access*/
421 #define CD0_OR0_S 10 /* Outer region Cacheability for TT0 access*/
441 #define CD0_IR1_S 24 /* Inner region Cacheability for TT1 access*/
/freebsd/sys/arm64/arm64/
H A Dgic_v3_reg.h144 * Cacheability
196 * Cacheability
316 * Cacheability
386 * Cacheability
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v3.yaml112 and cacheability attributes but are connected to a non-coherent
205 cacheability attributes but is connected to a non-coherent
/freebsd/sys/dev/vt/hw/efifb/
H A Defifb.c110 * cacheability attributes before making a final decision. in vt_efifb_init()
/freebsd/sys/contrib/edk2/Include/Uefi/
H A DUefiSpec.h61 // Memory cacheability attributes
72 // protection attribute. Also, EFI_MEMORY_WP means cacheability attribute.
131 // Defines the bits reserved for describing optional ISA-specific cacheability
132 // attributes that are not covered by the standard UEFI Memory Attributes cacheability
/freebsd/sys/arm64/vmm/
H A Dvmm_arm64.c137 * SCTLR_EL2_C: Data cacheability not affected in arm_setup_vectors()
138 * SCTLR_EL2_I: Instruction cacheability not affected in arm_setup_vectors()
/freebsd/sys/riscv/riscv/
H A Dpmap.c546 * Holds the PTE mode bits (defined in pte.h) for defining e.g. cacheability.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsX86.td234 // Cacheability support ops
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxintrin.h3569 /* Cacheability support ops */