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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 &plic {
18 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
22 compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
26 compatible = "sophgo,cv1800-clk";
H A Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
18 &plic {
19 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
23 compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
27 compatible = "sophgo,cv1810-clk";
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
17 #address-cells = <2>;
18 #size-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cach
64 plic: interrupt-controller@10000000 { global() label
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/freebsd/sys/riscv/riscv/
H A Dplic.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of
52 #include <dt-bindings/interrupt-controller/irq.h>
70 (_sc->contexts[_cpu].enable_offset + ((_irq) / 32) * sizeof(uint32_t))
72 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_THRESHOLD)
74 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_CLAIM)
107 { "sifive,plic-1.0.0", 1 },
108 { "thead,c900-plic", 1 },
113 bus_read_4(sc->mem_res, (reg))
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/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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