| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| H A D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
40 st,fmc2-ebi-cs-mux-enable:
46 st,fmc2-ebi-cs-buswidth:
[all …]
|
| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
44 * Per lane register fields
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
66 /* RX lane power state control */
[all …]
|
| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * Per lane register fields
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
65 /* RX lane power state control */
74 /* TX lane power state control */
[all …]
|
| H A D | al_hal_serdes_25g_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
84 /* [0x14] Lane status */
94 struct al_serdes_c_lane lane[2]; /* [0x200] */ member
132 /* Bit-wise write enable */
139 * 0x1 – Select inter-macro reference clock from the left side
141 * 0x3 – Select inter-macro reference clock from the right side
156 * 0x2 – Select inter-macro reference clock input from right side
172 * 0x2 – Select inter-macro reference clock input from left side
186 * Program memory acknowledge - Only when the access
193 * Data memory acknowledge - Only when the access
[all …]
|
| H A D | al_hal_pcie.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
57 * - Interrupt Handling.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soundwire/ |
| H A D | qcom,soundwire.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/ |
| H A D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
355 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
360 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
365 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
370 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
375 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
380 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
355 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
360 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
365 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
370 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
375 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
380 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/ |
| H A D | lpc4350-hitex-eval.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
[all …]
|
| H A D | lpc4357-myd-lpc4357.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
|
| H A D | lpc4357-ea4357-devkit.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]
|
| /freebsd/sys/dev/sfxge/common/ |
| H A D | ef10_tlv_layout.h | 1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
48 * systems which are little-endian and do not do strange things with structure
49 * padding. (Big-endian host systems will require some byte-swapping.)
51 * -----
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
56 * -----
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
73 * - NNNN is an index of some form. Some item types are per-port, some
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 1 //===-- X86InstCombineIntrinsic.cpp - X86 specific InstCombine pass -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
31 VectorType *IntTy = VectorType::getInteger(cast<VectorType>(V->getType())); in getNegativeIsTrueBoolVec()
49 ExtMask->getType()->isIntOrIntVectorTy(1)) in getBoolVecFromMask()
63 // Zero Mask - masked load instruction creates a zero vector. in simplifyX86MaskedLoad()
68 // intrinsic to the LLVM intrinsic to allow target-independent optimizations. in simplifyX86MaskedLoad()
72 unsigned AddrSpace = cast<PointerType>(Ptr->getType())->getAddressSpace(); in simplifyX86MaskedLoad()
76 // The pass-through vector for an x86 masked load is a zero vector. in simplifyX86MaskedLoad()
[all …]
|
| H A D | X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "x86-isel"
74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
78 "alignment set by x86-experimental-pref-loop-alignment."),
82 "x86-br-merging-base-cost", cl::init(2),
88 "will be merged, and above which conditionals will be split. Set to -1 "
93 "x86-br-merging-ccmp-bias", cl::init(6),
[all …]
|
| H A D | X86ISelLowering.h | 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDKernelCodeT.h | 1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 //---------------------------------------------------------------------------//
18 //---------------------------------------------------------------------------//
87 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
91 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
95 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
99 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
[all …]
|
| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
75 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are re…
77 … 0x003828UL //Access:R DataWidth:0x20 // byte number of tlp sent
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // instructions to allow proper scheduling, if-conversion, and other late
12 // the post-regalloc scheduling pass.
14 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "arm-pseudo"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
126 // For quad-register load-lane and store-lane pseudo instructors, the
128 // OddDblSpc depending on the lane number operand.
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
34 /// MCRegisterClass - Base class of TargetRegisterClass.
51 /// getID() - Return the register class ID number.
55 /// begin/end - Return all of the registers in this class.
60 /// getNumRegs - Return the number of registers in this class.
64 /// getRegister - Return the specified register in the class.
71 /// contains - Return true if the specified register is included in this
[all …]
|
| /freebsd/sys/dev/bxe/ |
| H A D | bxe_elink.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
44 #define DEBUG_TYPE "wasm-lower"
49 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
59 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
65 if (Subtarget->hasSIMD128()) { in WebAssemblyTargetLowering()
73 if (Subtarget->hasHalfPrecision()) { in WebAssemblyTargetLowering()
76 if (Subtarget->hasReferenceTypes()) { in WebAssemblyTargetLowering()
[all …]
|
| /freebsd/contrib/libpcap/ |
| H A D | gencode.c | 45 #include "pcap-dos.h"
48 #include "pcap-int.h"
64 #include "diag-control.h"
75 #define offsetof(s, e) ((size_t)&((s *)0)->e)
152 #include "os-proto.h"
158 * "Push" the current value of the link-layer header type and link-layer
160 * full-blown stack; we keep only the top two items.)
164 (cs)->prevlinktype = (cs)->linktype; \
165 (cs)->off_prevlinkhdr = (cs)->off_linkhdr; \
166 (cs)->linktype = (new_linktype); \
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "asm-parser"
81 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
92 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
101 // of Mask, and so on downwards. So (5 - Position) will shift the in extractITMaskBit()
102 // right bit down to bit 0, including the always-0 bit at bit 4 for in extractITMaskBit()
104 return (Mask >> (5 - Position) & 1); in extractITMaskBit()
159 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) in emitPersonalityLocNotes()
[all …]
|
| /freebsd/sys/contrib/zlib/ |
| H A D | ChangeLog | 5 - Reject overflows of zip header fields in minizip
6 - Fix bug in inflateSync() for data held in bit buffer
7 - Add LIT_MEM define to use more memory for a small deflate speedup
8 - Fix decision on the emission of Zip64 end records in minizip
9 - Add bounds checking to ERR_MSG() macro, used by zError()
10 - Neutralize zip file traversal attacks in miniunz
11 - Fix a bug in ZLIB_DEBUG compiles in check_match()
12 - Various portability and appearance improvements
15 - Remove K&R function definitions and zlib2ansi
16 - Fix bug in deflateBound() for level 0 and memLevel 9
[all …]
|