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/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt1 IFM camera sensor interface on mpc5200 LocalPlus bus
4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
[all …]
/linux/drivers/media/platform/xilinx/
H A Dxilinx-vip.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include <dt-bindings/media/xilinx-vip.h>
20 #include "xilinx-vip.h"
22 /* -----------------------------------------------------------------------------
48 * xvip_get_format_by_code - Retrieve format information for a media bus code
49 * @code: the format media bus code
52 * given V4L2 media bus format @code, or ERR_PTR if no corresponding format can
62 if (format->code == code) in xvip_get_format_by_code()
[all …]
/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 * PC-Card window open in mrshpc_setup_windows()
25 /* common mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
34 /* attribute mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
37 /* attribute mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
44 __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
46 __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
[all …]
/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-tqmls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include "fsl-ls1088a.dtsi"
14 num-cs = <2>;
18 compatible = "jedec,spi-nor";
20 spi-max-frequency = <62500000>;
21 spi-rx-bus-width = <4>;
22 spi-tx-bus-width = <4>;
23 vcc-supply = <&reg_vcc1v8>;
[all …]
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
23 "#dma-cells":
28 - amd,versal2-dma-1.0
[all …]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt1 * Boot Bus
3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-torbreck.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
12 * NOTE: This file is completely based on original board file for mach-torbreck
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
34 pmic_ap_clk: clock-0 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
43 clock-frequency = <24000000>;
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dovti,ov772x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo@jmondi.org>
20 - ovti,ov7720
21 - ovti,ov7725
29 reset-gpios:
34 powerdown-gpios:
40 $ref: /schemas/graph.yaml#/$defs/port-base
46 $ref: /schemas/media/video-interfaces.yaml#
[all …]
H A Dovti,ov5642.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: /schemas/media/video-interface-devices.yaml#
25 AVDD-supply:
28 DVDD-supply:
31 DOVDD-supply:
34 powerdown-gpios:
38 reset-gpios:
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Datmel,ebi.txt3 The External Bus Interface (EBI) controller is a bus where you can connect
5 The EBI provides a glue-less interface to asynchronous memories through the SMC
10 - compatible: "atmel,at91sam9260-ebi"
11 "atmel,at91sam9261-ebi"
12 "atmel,at91sam9263-ebi0"
13 "atmel,at91sam9263-ebi1"
14 "atmel,at91sam9rl-ebi"
15 "atmel,at91sam9g45-ebi"
16 "atmel,at91sam9x5-ebi"
17 "atmel,sama5d3-ebi"
[all …]
H A Dmvebu-devbus.txt1 Device tree bindings for MVEBU Device Bus controllers
3 The Device Bus controller available in some Marvell's SoC allows to control
5 The actual devices are instantiated from the child nodes of a Device Bus node.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-evb-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
16 stdout-path = "serial0";
19 gpio-power {
20 compatible = "gpio-keys";
22 key-power {
26 linux,input-type = <EV_KEY>;
27 debounce-interval = <100>;
[all …]
H A Dcv1812h-huashan-pi.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <1>;
32 #size-cells = <1>;
37 no-map;
43 clock-frequency = <25000000>;
48 bus-width = <4>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Datmel-isi.txt2 ----------------------------------
5 - compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
6 - reg: physical base address and length of the registers set for the device.
7 - interrupts: should contain IRQ line for the ISI.
8 - clocks: list of clock specifiers, corresponding to entries in the clock-names
9 property; please refer to clock-bindings.txt.
10 - clock-names: required elements: "isi_clk".
11 - pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt.
13 ISI supports a single port node with parallel bus. It shall contain one
15 defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
[all …]
H A Dallwinner,sun4i-a10-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
13 description: |-
20 - const: allwinner,sun4i-a10-csi1
21 - const: allwinner,sun7i-a20-csi0
22 - items:
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-starscream.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,starscream-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
28 reserved-memory {
29 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dflctl-nand.txt4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "renesas,shmobile-flctl-sh7372";
[all …]
/linux/arch/powerpc/boot/dts/
H A Do2d.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 gpio-controller;
13 fsl,has-wdt;
14 fsl,wdt-on-boot = <0>;
16 &gpt1 { gpio-controller; };
33 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cell-index = <0>;
48 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt2 -------------------------------------
8 Each video IP core is represented by an AMBA bus child node in the device
10 cores are represented as defined in ../video-interfaces.txt.
12 The whole pipeline is represented by an AMBA bus child node in the device
16 -----------------
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
25 - xlnx,video-width: This property qualifies the video format with the sample
26 width expressed as a number of bits per pixel component. All components must
27 use the same width.
[all …]

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