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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 u32 cs_wr_off; /* Write deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
61 u32 wr_cycle; /* Total write cycle time */
97 u32 t_cez_w; /* write CS deassertion to high Z */
100 u32 t_wpl; /* write assertion time */
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
[all …]
/linux/drivers/dma/qcom/
H A Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
17 #include <linux/dma-mapping.h>
45 "maximum write burst (default: ACPI/DT value)");
50 "maximum read burst (default: ACPI/DT value)");
55 "maximum number of write transactions (default: ACPI/DT value)");
67 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
68 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
69 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
70 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
/linux/drivers/char/tpm/
H A Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
48 * struct tpm_i2c_cr50_priv_data - Driver private data.
63 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
77 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
79 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
[all …]
/linux/include/linux/mtd/
H A Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
51 * send cmd to flash or write single 16 bit word at a time.
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
37 if (chip->ops->pci_address) in dw_edma_get_pci_address()
38 return chip->ops->pci_address(chip->dev, cpu_addr); in dw_edma_get_pci_address()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
97 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
134 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
148 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
[all …]
/linux/arch/sparc/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
50 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
58 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
62 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
66 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
75 /* Values describing the burst-size property from the PROM */
/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
21 u32 stride; /* bit 31:16 write stride
79 u32 control; /* Read/Write */
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
85 * bit 15:0 - read sequence number
/linux/drivers/media/dvb-frontends/
H A Dcx24116.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
5 Copyright (C) 2006-2008 Steven Toth <stoth@hauppauge.com>
6 Copyright (C) 2006-2007 Georg Acher
7 Copyright (C) 2007-2008 Darron Broad
45 #define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
74 /* Select DVB-S demodulator, else DVB-S2 */
115 /* DiSEqC burst */
119 /* DiSEqC tone burst */
128 MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_sup.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
18 * qla2x00_lock_nvram_access() -
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_lock_nvram_access()
28 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
31 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
35 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
36 rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
38 data = rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
42 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
[all …]
/linux/drivers/ata/
H A Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
141 * Set Mem Addr Read, Write ID for data transfers in ahci_ceva_setup()
142 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()
150 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()
164 writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); in ahci_ceva_setup()
167 writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); in ahci_ceva_setup()
[all …]
/linux/drivers/rtc/
H A Drtc-max6900.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define MAX6900_REG_SC 0 /* seconds 00-59 */
22 #define MAX6900_REG_MN 1 /* minutes 00-59 */
23 #define MAX6900_REG_HR 2 /* hours 00-23 */
24 #define MAX6900_REG_DT 3 /* day of month 00-31 */
25 #define MAX6900_REG_MO 4 /* month 01-12 */
26 #define MAX6900_REG_DW 5 /* day of week 1-7 */
27 #define MAX6900_REG_YR 6 /* year 00-99 */
33 #define MAX6900_BURST_LEN 8 /* can burst r/w first 8 regs */
35 #define MAX6900_REG_CT_WP (1 << 7) /* Write Protect */
[all …]
H A Drtc-ds1302.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2003 - 2007 Paul Mundt
19 #define RTC_CMD_WRITE 0x80 /* Write command */
21 #define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
22 #define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
26 #define RTC_CLCK_BURST 0x1F /* Address of clock burst */
27 #define RTC_CLCK_LEN 0x08 /* Size of clock burst */
54 /* Write registers starting at the first time/date address. */ in ds1302_rtc_set_time()
58 *bp++ = bin2bcd(time->tm_sec); in ds1302_rtc_set_time()
59 *bp++ = bin2bcd(time->tm_min); in ds1302_rtc_set_time()
[all …]
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
32 * up of one or more DMA bursts. The DMA burst implementation mechanism is,
34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset
37 * writing threshold, SPICC starts a writing request burst, which reads the
38 * preset number of words from RXFIFO, then write them into RX buffer.
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dsh2007.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
40 /* burst count (0-3:4,8,16,32) */
46 /* RD hold for SRAM (0-1:0,1) */
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
52 /* Multiplex (0-1:0,1) */
[all …]
/linux/drivers/pcmcia/
H A Do2micro.h112 * 'reserved' register at 0x94/D4. allows setting read prefetch and write in o2micro_override()
115 * ok to write to both registers on all O2 bridges. in o2micro_override()
121 if (PCI_FUNC(socket->dev->devfn) == 0) { in o2micro_override()
124 dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b); in o2micro_override()
126 switch (socket->dev->device) { in o2micro_override()
128 * older bridges have problems with both read prefetch and write in o2micro_override()
151 dev_warn(&socket->dev->dev, in o2micro_override()
155 dev_info(&socket->dev->dev, in o2micro_override()
156 …"O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the… in o2micro_override()
162 dev_info(&socket->dev->dev, in o2micro_override()
[all …]
/linux/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 #define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
24 #define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
25 #define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
26 #define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
[all …]
/linux/tools/perf/pmu-events/arch/x86/bonnell/
H A Dother.json135 "BriefDescription": "Burst read bus transactions.",
143 "BriefDescription": "Burst read bus transactions.",
151 "BriefDescription": "Burst (full cache-line) bus transactions.",
159 "BriefDescription": "Burst (full cache-line) bus transactions.",
183 "BriefDescription": "Instruction-fetch bus transactions.",
191 "BriefDescription": "Instruction-fetch bus transactions.",
263 "BriefDescription": "Partial write bus transaction.",
271 "BriefDescription": "Partial write bus transaction.",

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