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/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 wireless and mobile applications that use low-power technology. The actual
21 pattern: "^memory-controller@[0-9a-f]+$"
25 - enum:
26 - fsl,imx1-weim
[all …]
/linux/arch/mips/lantiq/xway/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
13 #include <linux/clk.h>
38 #define DMA_PDEN BIT(6) /* enable packet drop */
44 #define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
47 #define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
48 #define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
[all …]
/linux/drivers/dma/qcom/
H A Dqcom_adm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
29 /* ADM registers - calculated from channel number and security domain */
99 #define ADM_MAX_XFER (SZ_64K - 1)
100 #define ADM_MAX_ROWS (SZ_64K - 1)
166 struct clk *core_clk;
167 struct clk *iface_clk;
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/linux/drivers/usb/host/
H A Dehci-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
40 struct clk *clk; member
46 #define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)->priv)
56 num_phys = of_count_phandle_with_args(dev->of_node, "phys", in exynos_ehci_get_phy()
57 "#phy-cells"); in exynos_ehci_get_phy()
59 phy = devm_of_phy_get_by_index(dev, dev->of_node, phy_number); in exynos_ehci_get_phy()
62 exynos_ehci->phy[phy_number] = phy; in exynos_ehci_get_phy()
68 for_each_available_child_of_node_scoped(dev->of_node, child) { in exynos_ehci_get_phy()
[all …]
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
[all …]
/linux/sound/soc/kirkwood/
H A Dkirkwood-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * kirkwood-i2s.c
6 * (c) 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
16 #include <linux/clk.h>
20 #include <linux/platform_data/asoc-kirkwood.h>
34 /* These registers are relative to the second register region -
56 struct device_node *np = pdev->dev.of_node; in armada_38x_i2s_init_quirk()
60 priv->pll_config = devm_platform_ioremap_resource_byname(pdev, "pll_regs"); in armada_38x_i2s_init_quirk()
61 if (IS_ERR(priv->pll_config)) in armada_38x_i2s_init_quirk()
62 return -ENOMEM; in armada_38x_i2s_init_quirk()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
[all …]
H A Dstm32-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
13 #include <linux/clk.h>
16 #include <linux/dma-mapping.h>
31 #include "../virt-dma.h"
49 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
72 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
74 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
75 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
[all …]
/linux/drivers/bus/
H A Dimx-weim.c11 #include <linux/clk.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
78 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
80 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
82 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
83 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
85 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
92 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
107 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); in imx_weim_gpr_setup()
109 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); in imx_weim_gpr_setup()
[all …]
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
50 * write to a page or burst memory
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
52 * read to a page or burst memory
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
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/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
28 to program the clk retiming.
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
/linux/drivers/dma/
H A Dnbpfaxi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
22 #include <dt-bindings/dma/nbpfaxi.h>
57 #define NBPF_CHAN_CFG_LOEN 0x10 /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
58 #define NBPF_CHAN_CFG_HIEN 0x20 /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
68 #define NBPF_CHAN_CFG_SBE 0x8000000 /* Sweep Buffer Enable */
71 #define NBPF_CHAN_CFG_REN 0x40000000 /* RM: Register Set Enable */
104 * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
[all …]
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
7 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-dwc-qos-eth.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
32 struct clk *clk_master;
33 struct clk *clk_slave;
34 struct clk *clk_tx;
35 struct clk *clk_rx;
43 struct device *dev = &pdev->dev; in dwc_eth_dwmac_config_dt()
48 if (!plat_dat->axi) { in dwc_eth_dwmac_config_dt()
[all …]
/linux/drivers/media/platform/marvell/
H A Dmcam-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
13 #include <media/v4l2-common.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-dev.h>
16 #include <media/videobuf2-v4l2.h>
129 struct clk *clk[NR_MCAM_CLK]; member
131 struct clk *mclk;
166 /* DMA buffers - vmalloc mode */
176 /* DMA buffers - DMA modes */
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 /* maximum burst len for dma (4 bytes unit) */
24 * must be low enough so that a DMA transfer of above burst length can
259 /* maximum dma burst size */
320 struct clk *mac_clk;
323 struct clk *phy_clk;
345 /* dma channel enable mask */
/linux/drivers/usb/phy/
H A Dphy-mv-usb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
70 u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
84 u8 b_bus_req; /* B-Device Require Bus */
108 u32 usbintr; /* Interrupt enable */
114 u32 burstsize; /* Programmable Burst Size */
115 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
118 u32 epnaken; /* Endpoint NAK Enable */
125 u32 epflush; /* Endpoint De-initialize */
131 u32 ier; /* Interrupt Enable */
157 struct clk *clk; member
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
34 description: Continuous clock enable (first bank must be configured
40 st,fmc2-ebi-cs-mux-enable:
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/linux/sound/soc/uniphier/
H A Daio.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2016-2018 Socionext Inc.
15 #include <sound/soc-dai.h>
43 /* IEC61937 Repetition period of data-burst in IEC60958 frames */
52 /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */
70 #define AUD_NAME_PCMIN1 "aio-pcmin1"
71 #define AUD_NAME_PCMIN2 "aio-pcmin2"
72 #define AUD_NAME_PCMIN3 "aio-pcmin3"
73 #define AUD_NAME_IECIN1 "aio-iecin1"
74 #define AUD_NAME_DIECIN1 "aio-diecin1"
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/drivers/usb/dwc3/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
20 #include <linux/dma-mapping.h>
37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
187 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
188 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
189 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
190 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
191 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
[all …]

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