Home
last modified time | relevance | path

Searched +full:burst +full:- +full:clk +full:- +full:enable (Results 1 – 25 of 145) sorted by relevance

123456

/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 wireless and mobile applications that use low-power technology. The actual
21 pattern: "^memory-controller@[0-9a-f]+$"
25 - enum:
26 - fsl,imx1-weim
[all …]
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
32 * up of one or more DMA bursts. The DMA burst implementation mechanism is,
34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset
37 * writing threshold, SPICC starts a writing request burst, which reads the
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
[all …]
H A Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
30 #include <linux/dma/imx-dma.h>
36 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
76 void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
105 struct clk *clk_per;
106 struct clk *clk_ipg;
138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
[all …]
/linux/sound/soc/kirkwood/
H A Dkirkwood-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * kirkwood-i2s.c
6 * (c) 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
16 #include <linux/clk.h>
20 #include <linux/platform_data/asoc-kirkwood.h>
34 /* These registers are relative to the second register region -
56 struct device_node *np = pdev->dev.of_node; in armada_38x_i2s_init_quirk()
60 priv->pll_config = devm_platform_ioremap_resource_byname(pdev, "pll_regs"); in armada_38x_i2s_init_quirk()
61 if (IS_ERR(priv->pll_config)) in armada_38x_i2s_init_quirk()
62 return -ENOMEM; in armada_38x_i2s_init_quirk()
[all …]
/linux/drivers/dma/
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
7 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
[all …]
H A Dnbpfaxi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
22 #include <dt-bindings/dma/nbpfaxi.h>
57 #define NBPF_CHAN_CFG_LOEN 0x10 /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
58 #define NBPF_CHAN_CFG_HIEN 0x20 /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
68 #define NBPF_CHAN_CFG_SBE 0x8000000 /* Sweep Buffer Enable */
71 #define NBPF_CHAN_CFG_REN 0x40000000 /* RM: Register Set Enable */
104 * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
[all …]
H A Dstm32-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
13 #include <linux/clk.h>
16 #include <linux/dma-mapping.h>
31 #include "../virt-dma.h"
49 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
72 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
74 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
75 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
[all …]
H A Dstm32-mdma.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
10 * Inspired by stm32-dma.c and dma-jz4780.c
14 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
33 #include "../virt-dma.h"
252 struct clk *clk; member
265 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()
281 return &chan->vchan.chan.dev->device; in chan2dev()
286 return mdma_dev->ddev.dev; in mdma2dev()
[all …]
/linux/drivers/bus/
H A Dimx-weim.c11 #include <linux/clk.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
78 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
80 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
82 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
83 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
85 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
92 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
107 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); in imx_weim_gpr_setup()
109 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); in imx_weim_gpr_setup()
[all …]
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
50 * write to a page or burst memory
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
52 * read to a page or burst memory
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
28 to program the clk retiming.
[all …]
H A Dthead,th1520-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD TH1520 GMAC Ethernet controller
10 - Drew Fustini <dfustini@tenstorrent.com>
14 https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
17 - Compliant with IEEE802.3 Specification
18 - IEEE 1588-2008 standard for precision networked clock synchronization
19 - Supports 10/100/1000Mbps data transfer rate
[all …]
/linux/drivers/media/platform/marvell/
H A Dmcam-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
13 #include <media/v4l2-common.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-dev.h>
16 #include <media/videobuf2-v4l2.h>
129 struct clk *clk[NR_MCAM_CLK]; member
131 struct clk *mclk;
166 /* DMA buffers - vmalloc mode */
176 /* DMA buffers - DMA modes */
[all …]
/linux/drivers/tty/serial/
H A Dsprd_serial.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
6 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dma/sprd-dma.h>
50 /* interrupt enable register and its BITs */
121 bool enable; member
133 struct clk *clk; member
162 return readl_relaxed(port->membase + offset); in serial_in()
168 writel_relaxed(value, port->membase + offset); in serial_out()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 /* maximum burst len for dma (4 bytes unit) */
24 * must be low enough so that a DMA transfer of above burst length can
259 /* maximum dma burst size */
320 struct clk *mac_clk;
323 struct clk *phy_clk;
345 /* dma channel enable mask */
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
34 description: Continuous clock enable (first bank must be configured
40 st,fmc2-ebi-cs-mux-enable:
[all …]
/linux/drivers/usb/phy/
H A Dphy-mv-usb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
70 u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
84 u8 b_bus_req; /* B-Device Require Bus */
108 u32 usbintr; /* Interrupt enable */
114 u32 burstsize; /* Programmable Burst Size */
115 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
118 u32 epnaken; /* Endpoint NAK Enable */
125 u32 epflush; /* Endpoint De-initialize */
131 u32 ier; /* Interrupt Enable */
157 struct clk *clk; member
/linux/sound/soc/uniphier/
H A Daio.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2016-2018 Socionext Inc.
15 #include <sound/soc-dai.h>
43 /* IEC61937 Repetition period of data-burst in IEC60958 frames */
52 /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */
70 #define AUD_NAME_PCMIN1 "aio-pcmin1"
71 #define AUD_NAME_PCMIN2 "aio-pcmin2"
72 #define AUD_NAME_PCMIN3 "aio-pcmin3"
73 #define AUD_NAME_IECIN1 "aio-iecin1"
74 #define AUD_NAME_DIECIN1 "aio-diecin1"
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
54 #define WRPCR_REGEN BIT(24) /* REGulator ENable */
55 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
83 struct clk *pllref_clk;
84 struct clk *pclk;
96 writel(val, dsi->base + reg); in dsi_write()
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/drivers/iio/adc/
H A Dlpc18xx_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Hardware triggers
9 * - Burst mode
10 * - Interrupts
11 * - DMA
14 #include <linux/clk.h>
46 struct clk *clk; member
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
[all …]

123456