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Searched +full:bt1 +full:- +full:syscon (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
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/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
20 #include <linux/mfd/syscon.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
124 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
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H A Dclk-ccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL clocks driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
25 #include <dt-bindings/clock/bt1-ccu.h>
27 #include "ccu-pll.h"
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
60 * DDR controller AXI-bus clocks. If they are gated the system will be
62 * of the corresponding subsystems. So until we aren't ready to re-initialize
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/linux/drivers/bus/
H A Dbt1-axi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 AXI-bus driver
19 #include <linux/mfd/syscon.h>
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
38 * @sys_regs: Baikal-T1 System Controller registers map.
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
66 dev_crit_ratelimited(axi->dev, in bt1_axi_isr()
67 "AXI-bus fault %d: %s at 0x%x%08x\n", in bt1_axi_isr()
68 atomic_inc_return(&axi->count), in bt1_axi_isr()
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/linux/Documentation/devicetree/bindings/pci/
H A Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
22 - $ref: /schemas/pci/snps,dw-pcie.yaml#
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/linux/drivers/memory/
H A Dbt1-l2-ctl.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CM2 L2-cache Control Block driver.
18 #include <linux/mfd/syscon.h>
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
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/linux/drivers/i2c/busses/
H A Di2c-designware-platdrv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk-provider.h>
21 #include <linux/mfd/syscon.h>
33 #include "i2c-designware-core.h"
37 return clk_get_rate(dev->clk) / KILO; in i2c_dw_get_clk_rate_khz()
57 ret = regmap_write(dev->sysmap, BT1_I2C_CTL, in bt1_i2c_read()
62 return regmap_read(dev->sysmap, BT1_I2C_DO, val); in bt1_i2c_read()
70 ret = regmap_write(dev->sysmap, BT1_I2C_DI, val); in bt1_i2c_write()
74 return regmap_write(dev->sysmap, BT1_I2C_CTL, in bt1_i2c_write()
90 dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent); in bt1_i2c_request_regs()
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