Searched +full:bt1 +full:- +full:l2 +full:- +full:ctl (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 L2-cache Control Block11 - Serge Semin <fancer.lancer@gmail.com>14 By means of the System Controller Baikal-T1 SoC exposes a few settings to15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T117 L2-cache controller block is responsible for the tuning. Its DT node is[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 * Baikal-T1 CM2 L2-cache Control Block driver.38 * struct l2_ctl - Baikal-T1 L2 Control block private data.40 * @sys_regs: Baikal-T1 System Controller registers map.49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.50 * @L2_WSSTALL: Way-select latency.61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.63 * @id: L2-cache stall field identifier.77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()[all …]
1 # SPDX-License-Identifier: GPL-2.06 obj-$(CONFIG_DDR) += jedec_ddr_data.o8 obj-$(CONFIG_OF) += of_memory.o10 obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o11 obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o12 obj-$(CONFIG_BRCMSTB_DPFE) += brcmstb_dpfe.o13 obj-$(CONFIG_BRCMSTB_MEMC) += brcmstb_memc.o14 obj-$(CONFIG_BT1_L2_CTL) += bt1-l2-ctl.o15 obj-$(CONFIG_TI_AEMIF) += ti-aemif.o16 obj-$(CONFIG_TI_EMIF) += emif.o[all …]