Searched +full:bt1 +full:- +full:l2 +full:- +full:ctl (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 L2-cache Control Block11 - Serge Semin <fancer.lancer@gmail.com>14 By means of the System Controller Baikal-T1 SoC exposes a few settings to15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T117 L2-cache controller block is responsible for the tuning. Its DT node is[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 L2-cache Control Block11 - Serge Semin <fancer.lancer@gmail.com>14 By means of the System Controller Baikal-T1 SoC exposes a few settings to15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T117 L2-cache controller block is responsible for the tuning. Its DT node is[all …]
1 /*-2 * SPDX-License-Identifier: BSD-3-Clause34 /*-130 [0 ... IPPROTO_MAX - 1] = rip6_input };132 [0 ... IPPROTO_MAX - 1] = rip6_ctlinput };158 if (error || !req->newptr) in sysctl_netinet6_intr_queue_maxlen() 193 if (error || !req->newpt in sysctl_netinet6_intr_direct_queue_maxlen() 312 ip6proto_register(uint8_t proto,ip6proto_input_t input,ip6proto_ctlinput_t ctl) ip6proto_register() argument 1188 struct bintime boottimebin, bt1; ip6_savecontrol_v4() local [all...]