| /linux/Documentation/firmware-guide/acpi/ |
| H A D | chromeos-acpi-device.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 .. flat-table:: Supported ACPI Objects
13 :header-rows: 1
15 * - Object
16 - Description
18 * - CHSW
19 - Chrome OS switch positions
21 * - HWID
22 - Chrome OS hardware ID
24 * - FWID
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| H A D | method-tracing.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 method tracing facility.
20 ACPICA provides method tracing capability. And two functions are
24 -----------
28 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
30 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
33 But when the particular layer/level is applied to the control method
37 logs when the control method evaluation is started, and disable the
38 detailed logging when the control method evaluation is stopped.
52 control method is being evaluated::
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| H A D | debug.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 Compile-time configuration
16 Boot- and run-time configuration
20 you're interested in. At boot-time, use the acpi.debug_layer and
21 acpi.debug_level kernel command line options. After boot, you can use the
32 You can set the debug_layer mask at boot-time using the acpi.debug_layer
33 command line argument, and you can change it after boot by writing values
59 those related to initialization, method execution, informational messages, etc.
66 You can set the debug_level mask at boot-time using the acpi.debug_level
67 command line argument, and you can change it after boot by writing values
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| /linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| H A D | hip04-bootwrapper.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Bootwrapper boot method
10 - Wei Xu <xuwei5@hisilicon.com>
12 description: Bootwrapper boot method (software protocol on SMP)
17 - const: hisilicon,hip04-bootwrapper
19 boot-method:
20 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /linux/arch/arm64/kernel/ |
| H A D | cpu_ops.c | 1 // SPDX-License-Identifier: GPL-2.0-only
46 if (!strcmp(name, (*ops)->name)) in cpu_get_ops()
64 pr_err("Failed to find device node for boot cpu\n"); in cpu_read_enable_method()
68 enable_method = of_get_property(dn, "enable-method", NULL); in cpu_read_enable_method()
71 * The boot CPU may not have an enable method (e.g. in cpu_read_enable_method()
72 * when spin-table is used for secondaries). in cpu_read_enable_method()
76 pr_err("%pOF: missing enable-method property\n", in cpu_read_enable_method()
84 * In ACPI systems the boot CPU does not require in cpu_read_enable_method()
85 * checking the enable method since for some in cpu_read_enable_method()
86 * boot protocol (ie parking protocol) it need not in cpu_read_enable_method()
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| /linux/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
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| /linux/Documentation/arch/arm64/ |
| H A D | arm-acpi.rst | 7 Base Boot Requirements) [1] specifications. Both BSA and BBR are publicly
23 industry-standard Arm systems, they also apply to more than one operating
25 ACPI and Linux only, on an Arm system -- that is, what Linux expects of
30 ----------------
33 exist in Linux for describing non-enumerable hardware, after all. In this
40 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
45 - ACPI’s OSPM defines a power management model that constrains what the
49 - In the enterprise server environment, ACPI has established bindings (such
55 - Choosing a single interface to describe the abstraction between a platform
61 - The new ACPI governance process works well and Linux is now at the same
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| H A D | cpu-hotplug.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 CPUs that were not available during boot to be added to the system later.
15 CPU Hotplug on physical systems - CPUs not present at boot
16 ----------------------------------------------------------
34 boot to discover the system wide supported features. ACPI's MADT GICC
42 CPU Hotplug on virtual systems - CPUs not enabled at boot
43 ---------------------------------------------------------
46 ever have can be described at boot. There are no power-domain considerations
63 that firmware wishes to disable either from boot (or later) should not be
65 bit set, to indicate they can be enabled later. The boot CPU must be marked as
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| H A D | acpi_object_usage.rst | 16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT,
24 - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT,
41 This table describes a non-maskable event, that is used by the platform
53 **Boot Error Record Table**
58 BOOT Signature Reserved (signature == "BOOT")
60 **simple BOOT flag table**
66 **Boot Graphics Resource Table**
68 Optional, not currently supported, with no real use-case for an
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| /linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm23550.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
8 #include "bcm2166x-common.dtsi"
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
21 clock-frequency = <1000000000>;
26 compatible = "arm,cortex-a7";
27 enable-method = "brcm,bcm23550";
28 secondary-boot-reg = <0x35004178>;
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| /linux/Documentation/arch/arm/ |
| H A D | booting.rst | 9 The following documentation is relevant to 2.4.18-rmk6 and beyond.
11 In order to boot ARM Linux, you require a boot loader, which is a small
12 program that runs before the main kernel. The boot loader is expected
16 Essentially, the boot loader should provide (as a minimum) the
28 ---------------------------
30 Existing boot loaders:
32 New boot loaders:
35 The boot loader is expected to find and initialise all RAM that the
39 the RAM in the machine, or any other method the boot loader designer
44 -----------------------------
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| /linux/Documentation/PCI/ |
| H A D | acpi-info.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 method for accessing PCI config space below it, the address space windows
34 know early in boot, before it can parse the ACPI namespace. If a new table
39 If the OS is expected to manage a non-discoverable device described via
50 These are all device-specific, non-architected things, so the only way a
52 the device-specific details. The host bridge registers also include ECAM
66 bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
67 With the exception of ECAM, the bridge register space is device-specific
78 PNP0C02 "motherboard" devices are basically a catch-all. There's no
84 The PCIe spec requires the Enhanced Configuration Access Method (ECAM)
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| /linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra186-p3310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 phy: ethernet-phy@0 {
48 compatible = "ethernet-phy-ieee802.3-c22";
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| H A D | tegra210-p2180.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
18 stdout-path = "serial0:115200n8";
27 vdd-supply = <&vdd_gpu>;
33 /delete-property/ dmas;
34 /delete-property/ dma-names;
39 /delete-property/ reg-shift;
41 compatible = "nvidia,tegra30-hsuart";
42 reset-names = "serial";
45 compatible = "brcm,bcm43540-bt";
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| /linux/Documentation/arch/riscv/ |
| H A D | boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
12 touching the early boot process. For the purposes of this document, the
13 ``early boot process`` refers to any code that runs before the final virtual
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
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| /linux/arch/arm64/include/asm/ |
| H A D | cpu_ops.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * struct cpu_operations - Callback operations for hotplugging CPUs.
15 * enable-method property. On systems booting with ACPI, @name
17 * the boot protocol specified in the ACPI MADT table.
18 * @cpu_init: Reads any data necessary for a specific enable-method for a
20 * @cpu_prepare: Early one-time preparation step for a cpu. If there is a
21 * mechanism for doing so, tests whether it is possible to boot
24 * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary
27 * mechanism-specific information.
28 * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific
|
| /linux/Documentation/virt/kvm/s390/ |
| H A D | s390-pv-boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 s390 (IBM Z) Boot/IPL of Protected VMs
8 -------
13 Documentation/virt/kvm/s390/s390-pv.rst for details."
15 On IPL (boot) a small plaintext bootloader is started, which provides
28 executables and data via every available method (network, dasd, scsi,
29 direct kernel, ...) without the need to change the boot process.
33 -------
36 IPL information blocks, that specify the IPL method/devices and
46 The new PV load-device-specific-parameters field specifies all data
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| /linux/arch/arm/mach-orion5x/ |
| H A D | board-mss2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/mach-types.h>
17 #include "bridge-regs.h"
32 * Check for devices with hard-wired IRQs. in mss2_pci_map_irq()
35 if (irq != -1) in mss2_pci_map_irq()
38 return -1; in mss2_pci_map_irq()
58 * MSS2 power off method
62 * - Userland modifies U-boot env to tell U-boot to go idle at next boot
63 * - The board reboots
64 * - U-boot starts and go into an idle mode until the user press "power"
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| /linux/Documentation/arch/x86/ |
| H A D | microcode.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
8 - Borislav Petkov <bp@suse.de>
9 - Ashok Raj <ashok.raj@intel.com>
13 updating the microcode on platforms beyond the OEM End-Of-Life support,
14 and updating the microcode on long-running systems without rebooting.
21 The kernel can update microcode very early during boot. Loading
23 kernel boot time.
25 The microcode is stored in an initrd file. During boot, it is read from
30 loader parses the combined initrd image during boot.
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| /linux/Documentation/admin-guide/acpi/ |
| H A D | ssdt-overlays.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 In order to support ACPI open-ended hardware configurations (e.g. development
46 Method (_CRS, 0, Serialized)
59 ASL Optimizing Compiler version 20140214-64 [Mar 29 2014]
60 Copyright (c) 2000 - 2014 Intel Corporation
62 ASL Input: minnomax.asl - 30 lines, 614 bytes, 7 keywords
63 AML Output: minnowmax.aml - 165 bytes, 6 named objects, 1 executable opcodes
90 mkdir -p kernel/firmware/acpi
95 find kernel | cpio -H newc --create > /boot/instrumented_initrd
96 cat /boot/initrd >>/boot/instrumented_initrd
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| /linux/drivers/platform/x86/ |
| H A D | asus-laptop.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * asus-laptop.c - Asus Laptop Support
5 * Copyright (C) 2002-2005 Julien Lerouge, 2003-2006 Karol Kozimor
6 * Copyright (C) 2006-2007 Corentin Chary
13 * Pontus Fuchs - Helper functions, cleanup
14 * Johann Wiesner - Small compile fixes
15 * John Belmonte - ACPI code for Toshiba laptop was a good starting point.
16 * Eric Burghard - LED display support for W1N
17 * Josh Green - Light Sens support
18 * Thomas Tuttle - His first patch for led support was very helpful
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| /linux/Documentation/driver-api/early-userspace/ |
| H A D | early_userspace_support.rst | 5 Last update: 2004-12-20 tlh
15 - gen_init_cpio, a program that builds a cpio-format archive
18 - initramfs, a chunk of code that unpacks the compressed cpio image
19 midway through the kernel boot process.
20 - klibc, a userspace C library, currently packaged separately, that is
23 The cpio file format used by initramfs is the "newc" (aka "cpio -H newc")
24 format, and is documented in the file "buffer-format.txt". There are
29 CPIO ARCHIVE method
30 -------------------
38 IMAGE BUILDING method
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| /linux/Documentation/power/ |
| H A D | video.rst | 5 2003-2006, Pavel Machek
11 boot video card. (Kernel usually does not even contain video card
12 driver -- vesafb and vgacon are widely used).
22 methods work on different systems, and no known method suits all of
26 whitelist of systems, and automatically selects working method for a
32 Currently, VBE_SAVE method (6 below) works on most
56 (5) radeon systems, where X can soft-boot your video card. You'll need
67 (7) on some systems, it is possible to boot most of kernel, and then
69 http://dev.gentoo.org/~marineam/patch-radeonfb-2.6.11-rc2-mm2.
72 do echo 3 > /sys/power/state && /usr/sbin/video_post - which will
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| /linux/drivers/firmware/efi/libstub/ |
| H A D | Makefile.zboot | 1 # SPDX-License-Identifier: GPL-2.0
3 # to be include'd by arch/$(ARCH)/boot/Makefile after setting
9 truncate -s $$(hexdump -s16 -n4 -e '"%u"' $<) $@
18 comp-type-y := gzip
19 zboot-method-y := gzip
20 zboot-size-len-y := 0
22 comp-type-$(CONFIG_KERNEL_ZSTD) := zstd
23 zboot-method-$(CONFIG_KERNEL_ZSTD) := zstd22_with_size
24 zboot-size-len-$(CONFIG_KERNEL_ZSTD) := 4
27 $(call if_changed,$(zboot-method-y))
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
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