| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | atmel,lcdc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
16 input buffer per layer that fetches pixels through the single bus host
17 interface and a look-up table to allow palletized display configurations. The
18 LCDC is programmable on a per layer basis, and supports different LCD
19 resolutions, window sizes, image formats and pixel depths.
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| H A D | cirrus,clps711x-fb.txt | 4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per
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| H A D | wm,wm8505-fb.txt | 2 -----------------------------------------------------
5 - compatible : "wm,wm8505-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - bits-per-pixel : bit depth of framebuffer (16 or 32)
10 - display-timings: see display-timing.txt for information
15 compatible = "wm,wm8505-fb";
17 bits-per-pixel = <16>;
19 display-timings {
20 native-mode = <&timing0>;
22 clock-frequency = <0>; /* unused but required */
[all …]
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| H A D | via,vt8500-fb.txt | 2 -----------------------------------------------------
5 - compatible : "via,vt8500-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - interrupts : framebuffer controller interrupt
8 - bits-per-pixel : bit depth of framebuffer (16 or 32)
11 - display-timings: see display-timing.txt for information
16 compatible = "via,vt8500-fb";
19 bits-per-pixel = <16>;
21 display-timings {
22 native-mode = <&timing0>;
[all …]
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| H A D | atmel,lcdc.txt | 2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 - reg : Should contain 1 register ranges(address and length).
15 - interrupts : framebuffer controller interrupt
[all …]
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| H A D | mxsfb.txt | 6 - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
7 Should be "fsl,imx28-lcdif" for i.MX28.
8 Should be "fsl,imx6sx-lcdif" for i.MX6SX.
9 Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
10 - reg: Address and length of the register set for LCDIF
11 - interrupts: Should contain LCDIF interrupt
12 - clocks: A list of phandle + clock-specifier pairs, one for each
13 entry in 'clock-names'.
14 - clock-names: A list of clock names. For MXSFB it should contain:
15 - "pix" for the LCDIF block clock
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | fsl,imx-fb.txt | 6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
20 - lcd-supply: Regulator for LCD supply voltage.
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
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| H A D | fsl,imx8qxp-dc-dither.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-dither.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 or 8 bits per RGB channel to a virtual resolution of 10 bits. The physical
21 The dither operation can be individually enabled or disabled for each pixel
25 - Liu Ying <victor.liu@nxp.com>
29 const: fsl,imx8qxp-dc-dither
35 - compatible
36 - reg
[all …]
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| H A D | fsl,imx-lcdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | fsl,imx8qxp-pixel-link.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
[all …]
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| H A D | adi,adv7511.txt | 2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
37 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
45 - adi,input-justification: The input bit justification ("left", "evenly",
48 - avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
[all …]
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| H A D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | UgaDraw.h | 6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
27 @param ColorDepth Number of bits per pixel, currently defined to be 32.
51 @param ColorDepth Number of bits per pixel, currently defined to be 32.
76 EFI_UGA_PIXEL Pixel; member
84 EfiUgaVideoFill, ///< Write data from the BltBuffer pixel (SourceX, SourceY)
85 ///< directly to every pixel of the video display rectangle
87 ///< Only one pixel will be used from the BltBuffer. Delta is NOT used.
115 @param[in] This - Protocol instance pointer.
116 @param[in] BltBuffer - Buffer containing data to blit into video buffer. This
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| H A D | GraphicsOutput.h | 6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
30 /// A pixel is 32-bits and byte zero represents red, byte one represents green,
38 /// A pixel is 32-bits and byte zero represents blue, byte one represents green,
46 /// The Pixel definition of the physical frame buffer.
74 /// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly
79 /// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask.
80 …/// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reser…
84 /// Defines the number of pixel elements per video memory line.
139 EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel; member
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | images | 2 #------------------------------------------------------------------------------
4 # images: file(1) magic for image formats (see also "iff", and "c-lang" for
9 # merging several one- and two-line files into here.
13 # Targa - matches `povray', `ppmtotga' and `xv' outputs
19 # Note: called by DROID "Truevision TGA Bitmap" version 1.0 via PUID x-fmt/367
23 # or theoretically 2-128 reserved for use by Truevision or 128-255 may be used for developer applic…
32 # Targa image data (strength=70=110-40) before some Commodore disc image (strength=70=70+0 ./c64) l…
35 !:strength -40
37 #>(2.S-2) belong !0x28632943
39 # skip some MPEG sequence *.vob and some CRI ADX audio with improbable interleave bits
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/vt8500/ |
| H A D | vt8500-bv07.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
8 /dts-v1/;
21 bits-per-pixel = <16>;
22 display-timings {
23 native-mode = <&timing0>;
24 timing0: timing-800x480 {
25 clock-frequency = <0>; /* unused but required */
28 hfront-porch = <40>;
29 hback-porch = <88>;
[all …]
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| H A D | wm8650-mid.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
8 /dts-v1/;
12 model = "Wondermedia WM8650-MID Tablet";
21 bits-per-pixel = <16>;
23 display-timings {
24 native-mode = <&timing0>;
25 timing0: timing-800x480 {
26 clock-frequency = <0>; /* unused but required */
29 hfront-porch = <40>;
[all …]
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| H A D | wm8505-ref.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
8 /dts-v1/;
21 bits-per-pixel = <32>;
22 display-timings {
23 native-mode = <&timing0>;
24 timing0: timing-800x480 {
25 clock-frequency = <0>; /* unused but required */
28 hfront-porch = <40>;
29 hback-porch = <88>;
[all …]
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| H A D | wm8850-w70v2.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8850-w70v2.dts
4 * - Device tree file for Wondermedia WM8850 Tablet
5 * - 'W70-V2' mainboard
6 * - HongLianYing 'HLY070ML268-21A' 7" LCD panel
11 /dts-v1/;
13 #include <dt-bindings/pwm/pwm.h>
16 model = "Wondermedia WM8850-W70v2 Tablet";
19 compatible = "pwm-backlight";
22 brightness-levels = <0 40 60 80 100 130 190 255>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
10 compatible = "eukrea,mbimxsd25-baseboar
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| H A D | imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
10 compatible = "eukrea,mbimxsd25-baseboar
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| H A D | imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
10 compatible = "eukrea,mbimxsd25-baseboar
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| /freebsd/sys/contrib/device-tree/Bindings/display/tilcdc/ |
| H A D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | ovti,ov08x40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
15 - Automatic black level calibration (ABLC)
16 - Programmable controls for frame rate, mirror and flip, binning, cropping
18 - Output formats 10-bit 4C RGB RAW, 10-bit Bayer RAW
19 - 4-lane MIPI D-PHY TX @ 1 Gbps per lane
20 - 2-lane MPIP D-PHY TX @ 2 Gbps per lane
21 - Dynamic defect pixel cancellation
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
| H A D | video.txt | 2 -------------------------------------
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
25 - xlnx,video-width: This property qualifies the video format with the sample
26 width expressed as a number of bits per pixel component. All components must
29 - xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property
|