/linux/drivers/clk/stm32/ |
H A D | stm32mp13_rcc.h | 238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) 241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) 244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0) 257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) 258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) 261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0) 262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1) 263 #define RCC_BR_RSTSCLRR_PADRSTF BIT(2) 264 #define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) 265 #define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) [all …]
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/linux/drivers/platform/x86/intel/pmc/ |
H A D | mtl.c | 31 {"PMC", BIT(0)}, 32 {"OPI", BIT(1)}, 33 {"SPI", BIT(2)}, 34 {"XHCI", BIT(3)}, 35 {"SPA", BIT(4)}, 36 {"SPB", BIT(5)}, 37 {"SPC", BIT(6)}, 38 {"GBE", BIT(7)}, 40 {"SATA", BIT(0)}, 41 {"DSP0", BIT(1)}, [all …]
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H A D | adl.c | 15 {"SPI/eSPI", BIT(2)}, 16 {"XHCI", BIT(3)}, 17 {"SPA", BIT(4)}, 18 {"SPB", BIT(5)}, 19 {"SPC", BIT(6)}, 20 {"GBE", BIT(7)}, 22 {"SATA", BIT(0)}, 23 {"HDA_PGD0", BIT(1)}, 24 {"HDA_PGD1", BIT(2)}, 25 {"HDA_PGD2", BIT(3)}, [all …]
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H A D | tgl.c | 22 {"PSF9", BIT(0)}, 23 {"RES_66", BIT(1)}, 24 {"RES_67", BIT(2)}, 25 {"RES_68", BIT(3)}, 26 {"RES_69", BIT(4)}, 27 {"RES_70", BIT(5)}, 28 {"TBTLSX", BIT(6)}, 43 {"USB2PLL_OFF_STS", BIT(18)}, 44 {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)}, 45 {"PCIe_Gen3PLL_OFF_STS", BIT(20)}, [all …]
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/linux/drivers/crypto/intel/qat/qat_common/ |
H A D | adf_gen4_ras.h | 11 #define ADF_GEN4_ERRSOU0_BIT BIT(0) 18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0) 19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1) 20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2) 21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3) 22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4) 51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error 52 * BIT(4) - ri_tlq_phdr parity error 53 * BIT(5) - ri_tlq_pdata parity error 54 * BIT(6) - ri_tlq_nphdr parity error [all …]
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/linux/drivers/gpu/drm/mcde/ |
H A D | mcde_dsi_regs.h | 8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0) 9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1) 10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2) 11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3) 12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4) 13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5) 14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6) 15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7) 16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8) 17 #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(9) [all …]
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/linux/arch/mips/include/asm/mach-ath79/ |
H A D | ar71xx_regs.h | 171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31) 172 #define QCA956X_MAC_CFG1_RX_RST BIT(19) 173 #define QCA956X_MAC_CFG1_TX_RST BIT(18) 174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8) 175 #define QCA956X_MAC_CFG1_RX_EN BIT(2) 176 #define QCA956X_MAC_CFG1_TX_EN BIT(0) 179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9) 180 #define QCA956X_MAC_CFG2_IF_10_100 BIT(8) 181 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5) 182 #define QCA956X_MAC_CFG2_LEN_CHECK BIT(4) [all …]
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/linux/drivers/net/ethernet/freescale/dpaa2/ |
H A D | dpkg.h | 64 #define NH_FLD_ETH_DA BIT(0) 65 #define NH_FLD_ETH_SA BIT(1) 66 #define NH_FLD_ETH_LENGTH BIT(2) 67 #define NH_FLD_ETH_TYPE BIT(3) 68 #define NH_FLD_ETH_FINAL_CKSUM BIT(4) 69 #define NH_FLD_ETH_PADDING BIT(5) 70 #define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1) 73 #define NH_FLD_VLAN_VPRI BIT(0) 74 #define NH_FLD_VLAN_CFI BIT(1) 75 #define NH_FLD_VLAN_VID BIT(2) [all …]
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/linux/drivers/net/dsa/microchip/ |
H A D | ksz9477_reg.h | 43 #define SW_GIGABIT_ABLE BIT(6) 44 #define SW_REDUNDANCY_ABLE BIT(5) 45 #define SW_AVB_ABLE BIT(4) 63 #define SW_QW_ABLE BIT(5) 69 #define LUE_INT BIT(31) 70 #define TRIG_TS_INT BIT(30) 71 #define APB_TIMEOUT_INT BIT(29) 82 #define SW_SPARE_REG_2 BIT(7) 83 #define SW_SPARE_REG_1 BIT(6) 84 #define SW_SPARE_REG_0 BIT(5) [all …]
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/linux/sound/soc/codecs/ |
H A D | mt6357.h | 14 /* Reg bit defines */ 16 #define MT6357_GPIO8_DIR_MASK BIT(8) 18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8) 19 #define MT6357_GPIO9_DIR_MASK BIT(9) 21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9) 22 #define MT6357_GPIO10_DIR_MASK BIT(10) 24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10) 25 #define MT6357_GPIO11_DIR_MASK BIT(11) 27 #define MT6357_GPIO11_DIR_OUTPUT BIT(11) 28 #define MT6357_GPIO12_DIR_MASK BIT(12) [all …]
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/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ |
H A D | sun8i_a83t_mipi_csi2_reg.h | 14 #define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N BIT(31) 24 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL BIT(28) 25 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC3 BIT(27) 26 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC2 BIT(26) 27 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC1 BIT(25) 28 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC0 BIT(24) 29 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT3 BIT(23) 30 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT2 BIT(22) 31 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT1 BIT(21) 32 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_SEQ_ERR_DT0 BIT(20) [all …]
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/linux/include/linux/mfd/abx500/ |
H A D | ab8500-sysctrl.h | 83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0) 84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1) 85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2) 86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3) 87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4) 88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5) 89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6) 91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0) 92 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2) 97 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0) [all …]
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/linux/drivers/net/wireless/realtek/rtl8xxxu/ |
H A D | regs.h | 10 #define SYS_ISO_MD2PP BIT(0) 11 #define SYS_ISO_ANALOG_IPS BIT(5) 12 #define SYS_ISO_DIOR BIT(9) 13 #define SYS_ISO_PWC_EV25V BIT(14) 14 #define SYS_ISO_PWC_EV12V BIT(15) 17 #define SYS_FUNC_BBRSTB BIT(0) 18 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 19 #define SYS_FUNC_USBA BIT(2) 20 #define SYS_FUNC_UPLL BIT(3) 21 #define SYS_FUNC_USBD BIT(4) [all …]
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/linux/drivers/usb/typec/tcpm/ |
H A D | fusb302_reg.h | 13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7) 14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6) 15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5) 16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4) 17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3) 18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2) 19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1) 20 #define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0) 22 #define FUSB_REG_SWITCHES1_POWERROLE BIT(7) 23 #define FUSB_REG_SWITCHES1_SPECREV1 BIT(6) [all …]
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/linux/include/linux/mfd/ |
H A D | rohm-bd71815.h | 236 #define BD71815_BUCK_PWM_FIXED BIT(4) 237 #define BD71815_BUCK_SNVS_ON BIT(3) 238 #define BD71815_BUCK_RUN_ON BIT(2) 239 #define BD71815_BUCK_LPSR_ON BIT(1) 240 #define BD71815_BUCK_SUSP_ON BIT(0) 243 #define BD71815_BUCK_DVSSEL BIT(7) 244 #define BD71815_BUCK_STBY_DVS BIT(6) 257 #define LED_CHGDONE_EN BIT(4) 258 #define LED_RUN_ON BIT(2) 259 #define LED_LPSR_ON BIT(1) [all …]
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H A D | lp873x.h | 68 #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3) 69 #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2) 70 #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1) 71 #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0) 76 #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3) 77 #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2) 78 #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1) 79 #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0) 88 #define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2) 89 #define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1) [all …]
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H A D | lp87565.h | 97 #define LP87565_BUCK_CTRL_1_EN BIT(7) 98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6) 101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3) 102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2) 103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1) 105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0) 119 #define LP87565_RESET_SW_RESET BIT(0) 121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7) 122 #define LP87565_CONFIG_CLKIN_PD BIT(6) 123 #define LP87565_CONFIG_EN4_PD BIT(5) [all …]
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/linux/drivers/net/ethernet/mediatek/ |
H A D | mtk_wed_regs.h | 7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8) 10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) 11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16) 13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) 14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) 16 #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29) 17 #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31) 29 #define MTK_WED_RESET_TX_BM BIT(0) 30 #define MTK_WED_RESET_RX_BM BIT(1) 31 #define MTK_WED_RESET_RX_PG_BM BIT(2) [all …]
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/linux/include/linux/ |
H A D | hwmon.h | 51 #define HWMON_C_TEMP_RESET_HISTORY BIT(hwmon_chip_temp_reset_history) 52 #define HWMON_C_IN_RESET_HISTORY BIT(hwmon_chip_in_reset_history) 53 #define HWMON_C_CURR_RESET_HISTORY BIT(hwmon_chip_curr_reset_history) 54 #define HWMON_C_POWER_RESET_HISTORY BIT(hwmon_chip_power_reset_history) 55 #define HWMON_C_REGISTER_TZ BIT(hwmon_chip_register_tz) 56 #define HWMON_C_UPDATE_INTERVAL BIT(hwmon_chip_update_interval) 57 #define HWMON_C_ALARMS BIT(hwmon_chip_alarms) 58 #define HWMON_C_SAMPLES BIT(hwmon_chip_samples) 59 #define HWMON_C_CURR_SAMPLES BIT(hwmon_chip_curr_samples) 60 #define HWMON_C_IN_SAMPLES BIT(hwmon_chip_in_samples) [all …]
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/linux/drivers/comedi/drivers/ |
H A D | ni_stc.h | 25 #define NISTC_INTA_ACK_G0_GATE BIT(15) 26 #define NISTC_INTA_ACK_G0_TC BIT(14) 27 #define NISTC_INTA_ACK_AI_ERR BIT(13) 28 #define NISTC_INTA_ACK_AI_STOP BIT(12) 29 #define NISTC_INTA_ACK_AI_START BIT(11) 30 #define NISTC_INTA_ACK_AI_START2 BIT(10) 31 #define NISTC_INTA_ACK_AI_START1 BIT(9) 32 #define NISTC_INTA_ACK_AI_SC_TC BIT(8) 33 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7) 34 #define NISTC_INTA_ACK_G0_TC_ERR BIT(6) [all …]
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/linux/drivers/net/ethernet/asix/ |
H A D | ax88796c_main.h | 121 #define AX_FC_RX BIT(0) 122 #define AX_FC_TX BIT(1) 123 #define AX_FC_ANEG BIT(2) 126 #define AX_CAP_COMP BIT(0) 153 #define PSR_DEV_READY BIT(7) 155 #define PSR_RESET_CLR BIT(15) 158 #define FER_IPALM BIT(0) 159 #define FER_DCRC BIT(1) 160 #define FER_RH3M BIT(2) 161 #define FER_HEADERSWAP BIT(7) [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | sil-sii8620.h | 35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7) 36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6) 37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5) 38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4) 39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3) 40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2) 41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1) 42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0) 46 #define BIT_DPD_PWRON_PLL BIT(7) 47 #define BIT_DPD_PDNTX12 BIT(6) [all …]
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/linux/drivers/staging/sm750fb/ |
H A D | ddk750_reg.h | 7 #define DE_STATE1_DE_ABORT BIT(0) 10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3) 11 #define DE_STATE2_DE_STATUS_BUSY BIT(2) 12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) 20 #define SYSTEM_CTRL_PCI_BURST BIT(29) 21 #define SYSTEM_CTRL_PCI_MASTER BIT(25) 22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) 23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) 24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) 25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) [all …]
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
H A D | reg.h | 302 #define RXDMA_AGG_EN BIT(7) 306 /* Regsiter Bit and Content definition */ 308 #define ISO_MD2PP BIT(0) 309 #define ISO_PA2PCIE BIT(3) 310 #define ISO_PLL2MD BIT(4) 311 #define ISO_PWC_DV2RP BIT(11) 312 #define ISO_PWC_RV2RP BIT(12) 315 #define FEN_MREGEN BIT(15) 316 #define FEN_DCORE BIT(11) 317 #define FEN_CPUEN BIT(10) [all …]
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/linux/drivers/net/wireless/mediatek/mt76/ |
H A D | mt76_connac2_mac.h | 46 #define MT_TX_FREE_PAIR BIT(31) 55 #define MT_TXD1_LONG_FORMAT BIT(31) 56 #define MT_TXD1_TGID BIT(30) 58 #define MT_TXD1_AMSDU BIT(23) 63 #define MT_TXD1_ETH_802_3 BIT(15) 64 #define MT_TXD1_VTA BIT(10) 67 #define MT_TXD2_FIX_RATE BIT(31) 68 #define MT_TXD2_FIXED_RATE BIT(30) 72 #define MT_TXD2_HTC_VLD BIT(13) 73 #define MT_TXD2_DURATION BIT(12) [all …]
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