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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dspec_operation.json16 "BriefDescription": "This event counts every speculatively executed micro-operation."
20 … "BriefDescription": "This event counts architecturally executed load-exclusive instructions."
24 … "BriefDescription": "This event counts architecturally executed store-exclusive instructions."
28 …"BriefDescription": "This event counts architecturally executed memory-reading instructions, as de…
32 …"BriefDescription": "This event counts architecturally executed memory-writing instructions, as de…
36 …ription": "This event counts architecturally executed memory-reading instructions and memory-writi…
40 …"BriefDescription": "This event counts architecturally executed integer data-processing instructio…
44 …"BriefDescription": "This event counts architecturally executed Advanced SIMD data-processing inst…
48 …"BriefDescription": "This event counts architecturally executed floating-point data-processing ins…
68 …ch instructions that includes software change of the PC other than exception-generating instructio…
[all …]
/linux/include/linux/
H A Dassoc_array.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * See Documentation/core-api/assoc_array.rst for information.
28 * Operations on objects and index keys for use by array manipulation routines.
31 /* Method to get a chunk of an index key from caller-supplied data */
40 /* How different is an object from an index key, to a bit position in
41 * their keys? (or -1 if they're the same)
50 * Access and manipulation functions.
56 array->root = NULL; in assoc_array_init()
57 array->nr_leaves_on_tree = 0; in assoc_array_init()
/linux/Documentation/arch/riscv/
H A Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
[all …]
/linux/fs/xfs/libxfs/
H A Dxfs_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * XFS bit manipulation routines.
14 * masks with n high/low bits set, 64-bit values
18 return (uint64_t)-1 << (64 - (n)); in xfs_mask64hi()
22 return ((uint32_t)1 << (n)) - 1; in xfs_mask32lo()
26 return ((uint64_t)1 << (n)) - 1; in xfs_mask64lo()
29 /* Get high bit set out of 32-bit argument, -1 if none set */
32 return fls(v) - 1; in xfs_highbit32()
35 /* Get high bit set out of 64-bit argument, -1 if none set */
38 return fls64(v) - 1; in xfs_highbit64()
[all …]
H A Dxfs_bit.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2005 Silicon Graphics, Inc.
11 * XFS bit manipulation routines, used in non-realtime code.
17 * Returns 1 for empty, 0 for non-empty.
33 * Count the number of contiguous bits set in the bitmap starting with bit
46 size -= start_bit & ~(NBWORD - 1); in xfs_contig_bits()
47 start_bit &= (NBWORD - 1); in xfs_contig_bits()
51 tmp |= (~0U >> (NBWORD-start_bit)); in xfs_contig_bits()
55 size -= NBWORD; in xfs_contig_bits()
61 size -= NBWORD; in xfs_contig_bits()
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/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dadjust_pc.h1 // SPDX-License-Identifier: GPL-2.0-only
3 * Guest PC manipulation helpers
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Copyright (C) 2020 - Google LLC
36 vcpu_gp_regs(vcpu)->pstate = read_sysreg_el2(SYS_SPSR); in __kvm_skip_instr()
40 write_sysreg_el2(vcpu_gp_regs(vcpu)->pstate, SYS_SPSR); in __kvm_skip_instr()
46 * Assumes host is always 64-bit.
/linux/security/
H A DKconfig.hardening1 # SPDX-License-Identifier: GPL-2.0-only
7 def_bool $(cc-option,-ftrivial-auto-var-init=pattern)
10 def_bool $(cc-optio
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/linux/drivers/gpio/
H A Dgpio-xtensa.c1 // SPDX-License-Identifier: GPL-2.0
12 * GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE)
13 * output state called EXPSTATE, and 32bit input wire called IMPWIRE. This
18 * disables access to all coprocessors. This driver sets the CPENABLE bit
25 * would need to have a per core workqueue to do the actual GPIO manipulation.
48 xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable); in enable_cp()
86 return !!(impwire & BIT(offset)); in xtensa_impwire_get_value()
103 return !!(expstate & BIT(offset)); in xtensa_expstate_get_value()
110 u32 mask = BIT(offset); in xtensa_expstate_set_value()
111 u32 val = value ? BIT(offset) : 0; in xtensa_expstate_set_value()
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/linux/fs/xfs/
H A Dxfs_bmap_util.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2006 Silicon Graphics, Inc.
30 return -EFSCORRUPTED; in xfs_bmap_rtalloc()
40 __s64 bmv_block; /* starting block (64-bit daddr_t) */
67 /* EOF block manipulation functions */
/linux/include/linux/soc/ti/
H A Dknav_dma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * PKTDMA descriptor manipulation macros for host packet descriptor
17 #define MASK(x) (BIT(x) - 1)
20 #define KNAV_DMA_DESC_PS_INFO_IN_SOP BIT(22)
27 #define KNAV_DMA_DESC_HAS_EPIB BIT(31)
175 return -EINVAL; in knav_dma_get_flow()
/linux/arch/x86/include/asm/
H A Dpgtable-2level.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 return __pte(xchg(&xp->pte_low, 0)); in native_ptep_get_and_clear()
76 /* Bit manipulation helper on pte/pgoff entry */
91 * <----------------- offset ------------------> 0 E <- type --> 0
96 #define _SWP_TYPE_MASK ((1U << SWP_TYPE_BITS) - 1)
111 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
14 * bit is not displayed in /proc/cpuinfo at all.
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
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/linux/drivers/mtd/chips/
H A Dfwh_lock.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 struct cfi_private *cfi = map->fldrv_priv; in fwh_xxlock_oneblock()
37 if (chip->start < 0x400000) { in fwh_xxlock_oneblock()
38 pr_debug( "MTD %s(): chip->start: %lx wanted >= 0x400000\n", in fwh_xxlock_oneblock()
39 __func__, chip->start ); in fwh_xxlock_oneblock()
40 return -EIO; in fwh_xxlock_oneblock()
44 * - on 64k boundariesand in fwh_xxlock_oneblock()
45 * - bit 1 set high in fwh_xxlock_oneblock()
46 * - block lock registers are 4MiB lower - overflow subtract (danger) in fwh_xxlock_oneblock()
48 * The address manipulation is first done on the logical address in fwh_xxlock_oneblock()
[all …]
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
14 * bit is not displayed in /proc/cpuinfo at all.
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
[all …]
/linux/arch/riscv/crypto/
H A Daes-riscv64-zvkned-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
50 #include "aes-macros.S"
63 // LEN32 = number of blocks, rounded up, in 32-bit words.
68 // Create a mask that selects the last 32-bit word of each 128-bit
[all …]
H A Dsm4-riscv64-zvksed-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SM4 Block Cipher extension ('Zvksed')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
68 li t0, -4
76 addi a2, a2, -16
105 li t0, -4
[all …]
/linux/include/net/
H A Dneighbour.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Generic neighbour manipulation
17 * - Add neighbour cache statistics like rtstat
94 set_bit(index, p->data_state); in neigh_var_set()
95 p->data[index] = val; in neigh_var_set()
98 #define NEIGH_VAR(p, attr) ((p)->data[NEIGH_VAR_ ## attr])
108 bitmap_fill(p->data_state, NEIGH_VAR_DATA_MAX); in neigh_parms_data_state_setall()
113 bitmap_zero(p->data_state, NEIGH_VAR_DATA_MAX); in neigh_parms_data_state_cleanall()
136 #define NEIGH_CACHE_STAT_INC(tbl, field) this_cpu_inc((tbl)->stats->field)
194 * neighbour table manipulation
[all …]
/linux/drivers/input/mouse/
H A Dtrackpoint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 * Mode manipulation
67 #define TP_REACH 0x57 /* Backup for Z-axis press */
70 /* with Z-axis pressed) */
75 #define TP_THRESH 0x5C /* Minimum value for a Z-axis press */
76 #define TP_UP_THRESH 0x5A /* Used to generate a 'click' on Z-axis */
106 #define TP_TOGGLE_SOURCE_TAG 0x20 /* Bit 3 of the first packet will be set to
109 #define TP_TOGGLE_EXT_TAG 0x22 /* Bit 3 of the first packet coming from the
/linux/drivers/ptp/
H A Dptp_mock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Mock-up PTP Hardware Clock driver for virtual network devices
7 * Create a PTP clock which offers PTP time manipulation operations
15 /* Clamp scaled_ppm between -2,097,152,000 and 2,097,152,000,
16 * and thus "adj" between -68,719,476 and 68,719,476
29 * 64-bit overflow during the multiplication with cc->mult, given the max "adj"
57 spin_lock(&phc->lock); in mock_phc_adjfine()
58 timecounter_read(&phc->tc); in mock_phc_adjfine()
59 phc->cc.mult = MOCK_PHC_CC_MULT + adj; in mock_phc_adjfine()
60 spin_unlock(&phc->lock); in mock_phc_adjfine()
[all …]
/linux/fs/btrfs/
H A Dextent-io-tree.h1 /* SPDX-License-Identifier: GPL-2.0 */
63 * Bit not representing a state but a request for NOWAIT semantics,
81 * / EXTENT_CLEAR_DATA_RESV because they have special meaning to the bit
82 * manipulation functions
109 * owner == IO_TREE_INODE_IO - then inode is valid and fs_info can be
110 * accessed as inode->root->fs_info
170 bool btrfs_test_range_bit(struct extent_io_tree *tree, u64 start, u64 end, u32 bit,
172 bool btrfs_test_range_bit_exists(struct extent_io_tree *tree, u64 start, u64 end, u32 bit);
/linux/lib/crypto/riscv/
H A Dsha512-riscv64-zvknhb-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknhb')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
70 // Do 4 rounds of SHA-512. w0 contains the current 4 message schedule words.
73 // computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4
101 // message scheduling. There are 4 words, so an 8-bit mask suffices.
[all …]
/linux/arch/alpha/kernel/
H A Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * may also have PCI-PCI bridges present, and then we'd configure the
31 * a single bit set. This is so that devices like the broken Myrinet card
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
59 * avoid the HAE manipulation that would be needed.
73 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
79 * later) adheres to the PCI-PCI bridge specification. This says that
108 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
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/linux/net/sched/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 To administer these schedulers, you'll need the user-level utilities
54 in-depth articles.
74 Say Y here if you want to use an n-band priority queue packet
81 tristate "Hardware Multiqueue-aware Multi Band Queuing (MULTIQ)"
83 Say Y here if you want to use an n-band queue packet scheduler
199 re-ordering. This is often useful to simulate networks when
219 tristate "Multi-queue priority scheduler (MQPRIO)"
222 Say Y here if you want to use the Multi-queue Priority scheduler.
235 scheduler. This schedules packets according to skb->priority,
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/linux/drivers/crypto/caam/
H A Dpdb.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright 2008-2016 Freescale Semiconductor, Inc.
14 * PDB- IPSec ESP Header Modification Options
19 * Encap and Decap - Decrement TTL (Hop Limit) - Based on the value of the
27 * Decap - DiffServ Copy - Copy the IPv4 TOS or IPv6 Traffic Class byte
32 * Encap- Copy DF bit -if an IPv4 tunnel mode outer IP header is coming from
33 * the PDB, copy the DF bit from the inner IP header to the outer IP header.
47 * PDB - IPSec ESP Encap/Decap Options
50 #define PDBOPTS_ESP_ARS32 0x40 /* 32-entry antireplay window */
51 #define PDBOPTS_ESP_ARS128 0x80 /* 128-entry antireplay window */
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/linux/include/uapi/linux/
H A Dmroute6.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
50 #define ALL_MIFS ((mifi_t)(-1))
63 #define IF_SET(n, p) ((p)->ifs_bits[(n)/NIFBITS] |= (1 << ((n) % NIFBITS)))
64 #define IF_CLR(n, p) ((p)->ifs_bits[(n)/NIFBITS] &= ~(1 << ((n) % NIFBITS)))
65 #define IF_ISSET(n, p) ((p)->ifs_bits[(n)/NIFBITS] & (1 << ((n) % NIFBITS)))
70 * Passed by mrouted for an MRT_ADD_MIF - again we use the
85 * Cache manipulation structures for mrouted and PIMd
141 __u32 im6_pad; /* padding for 64 bit arch */
155 #define IP6MRA_CREPORT_MAX (__IP6MRA_CREPORT_MAX - 1)

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