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Searched +full:bias +full:- +full:ctrl +full:- +full:value (Results 1 – 25 of 29) sorted by relevance

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/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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/linux/drivers/media/usb/gspca/m5602/
H A Dm5602_ov9650.c1 // SPDX-License-Identifier: GPL-2.0-only
20 static int ov9650_s_ctrl(struct v4l2_ctrl *ctrl);
107 /* Enable HREF at optical black, enable ADBLC bias,
110 /* Subtract 32 from the B channel bias */
112 /* Subtract 32 from the Gb channel bias */
116 /* Subtract 32 from the R channel bias */
118 /* Subtract 32 from the R channel bias */
136 /* Set horizontal column start high to default value */
151 /* Enable denoise, and white-pixel erase */
307 return -ENODEV; in ov9650_probe()
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/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3-ctrls.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <media/media-entity.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
25 #include <media/v4l2-mediabus.h>
29 static int s5c73m3_get_af_status(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) in s5c73m3_get_af_status() argument
39 ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; in s5c73m3_get_af_status()
43 ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; in s5c73m3_get_af_status()
46 v4l2_info(&state->sensor_sd, "Unknown AF status %#x\n", reg); in s5c73m3_get_af_status()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "sc7180-firmware-tfa.dtsi"
22 thermal-zones {
23 charger_thermal: charger-thermal {
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
96 if (c->log_mask & dpu_hw_util_log_mask) in dpu_reg_write()
99 writel_relaxed(val, c->blk_addr + reg_off); in dpu_reg_write()
104 return readl_relaxed(c->blk_addr + reg_off); in dpu_reg_read()
128 lut_flags = (unsigned long) scaler3_cfg->lut_flag; in _dpu_hw_setup_scaler3_lut()
130 (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) { in _dpu_hw_setup_scaler3_lut()
131 lut[0] = scaler3_cfg->dir_lut; in _dpu_hw_setup_scaler3_lut()
135 (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && in _dpu_hw_setup_scaler3_lut()
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/linux/sound/pci/
H A Dens1370.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* Power-Management-Code ( CONFIG_PM )
11 * using https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-als
376 unsigned int ctrl; /* control register */ global() member
1521 unsigned int ctrl; snd_es1373_line_put() local
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
301 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
307 /* true if PHY default clk scheme is single-ended */
397 "vdd", "vdda-pll", "vdda-phy-dpdm",
402 /* struct override_param - structure holding qusb2 v2 phy overriding param
404 * to value
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/linux/arch/m68k/ifpsp060/src/
H A Dpfpsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
97 mov.l %d0,-(%sp)
98 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0
99 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
105 mov.l %d0,-(%sp)
106 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0
107 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
113 mov.l %d0,-(%sp)
114 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0
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H A Dfplsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
276 set LV, -LOCAL_SIZE # stack offset
285 set EXC_AREGS, -68 # offset of all address regs
286 set EXC_DREGS, -100 # offset of all data regs
287 set EXC_FPREGS, -36 # offset of all fp regs
373 set FTEMP_SGN, 2 # value saved in memory.
380 set LOCAL_SGN, 2 # value saved in memory.
387 set DST_HI, 4 # value saved in memory.
392 set SRC_HI, 4 # value saved in memory.
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H A Dfpsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
98 mov.l %d0,-(%sp)
99 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0
100 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
106 mov.l %d0,-(%sp)
107 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0
108 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
114 mov.l %d0,-(%sp)
115 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
58 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
110 * @dpb_longterm: DPB long-term
229 * @tile_r_info: per-tile information array
230 * @tile_c_info: per-tile information array
296 * @db_ctrl_col: db tile col ctrl buffer
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id()
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000e_get_phy_id()
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) in e1000e_get_phy_id()
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
48 * igb_get_phy_id - Retrieve the PHY ID and revision
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igb_get_phy_id()
68 phy->id = (u32)(phy_id << 16); in igb_get_phy_id()
70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igb_get_phy_id()
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H A Digb_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
56 "Copyright (c) 2007-2014 Intel Corporation.";
208 static int debug = -1;
220 {E1000_CTRL, "CTRL"},
253 /* igb_regdump - register printout routine */
260 switch (reginfo->ofs) { in igb_regdump()
310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); in igb_regdump()
314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); in igb_regdump()
315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], in igb_regdump()
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/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
377 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
380 writel(value, pcie->afi + offset); in afi_writel()
385 return readl(pcie->afi + offset); in afi_readl()
388 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
391 writel(value, pcie->pads + offset); in pads_writel()
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/linux/drivers/media/usb/gspca/
H A Dsonixb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2011 Jean-François Moine <http://moinejf.free.fr>
17 0x05 red gain 0-127
18 0x06 blue gain 0-127
19 0x07 green gain 0-127
21 0x08-0x0f i2c / 3wire registers
24 0x15 hsize (hsize = register-value * 16)
25 0x16 vsize (vsize = register-value * 16)
27 0x18 bit 7 enables compression, bit 4-5 set image down scaling:
29 0x19 high-nibble is sensor clock divider, changes exposure on sensors which
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/linux/drivers/net/wireless/ath/ath9k/
H A Deeprom_def.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
49 while (pcdac > ah->originalGain[i] && in ath9k_get_txgain_index()
50 i < (AR9280_TX_GAIN_TABLE_SIZE - 1)) in ath9k_get_txgain_index()
82 u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version); in ath9k_hw_def_get_eeprom_ver()
90 u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version); in ath9k_hw_def_get_eeprom_rev()
99 u16 *eep_data = (u16 *)&ah->eeprom.def; in __ath9k_hw_def_fill_eeprom()
113 u16 *eep_data = (u16 *)&ah->eeprom.def; in __ath9k_hw_usb_def_fill_eeprom()
128 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_def_fill_eeprom()
138 PR_EEP("Chain0 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[0])); in ath9k_def_dump_modal_eeprom()
139 PR_EEP("Chain1 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[1])); in ath9k_def_dump_modal_eeprom()
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H A Deeprom_9287.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
25 u16 version = le16_to_cpu(ah->eeprom.map9287.baseEepHeader.version); in ath9k_hw_ar9287_get_eeprom_ver()
33 u16 version = le16_to_cpu(ah->eeprom.map9287.baseEepHeader.version); in ath9k_hw_ar9287_get_eeprom_rev()
40 struct ar9287_eeprom *eep = &ah->eeprom.map9287; in __ath9k_hw_ar9287_fill_eeprom()
56 u16 *eep_data = (u16 *)&ah->eeprom.map9287; in __ath9k_hw_usb_ar9287_fill_eeprom()
72 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_ar9287_fill_eeprom()
82 PR_EEP("Chain0 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[0])); in ar9287_dump_modal_eeprom()
83 PR_EEP("Chain1 Ant. Control", le32_to_cpu(modal_hdr->antCtrlChain[1])); in ar9287_dump_modal_eeprom()
84 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ar9287_dump_modal_eeprom()
85 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); in ar9287_dump_modal_eeprom()
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/linux/drivers/video/fbdev/
H A Dimsttfb.c2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
40 #define eieio() /* Enforce In-order Execution of I/O */
135 * c is charge pump bias which depends on the VCO frequency
172 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
182 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
183 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
184 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
185 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
204 TVPIRCKL = 0x30, /* Color-Key Overlay Low */
205 TVPIRCKH = 0x31, /* Color-Key Overlay High */
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
22 #define AV1_REF_INVALID_SCALE -1
26 #define AV1_INVALID_IDX -1
28 #define AV1_DIV_ROUND_UP_POW2(value, n) \ argument
31 typeof(value) _value = value; \
35 #define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \ argument
38 typeof(value) _value_ = value; \
39 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
43 #define BIT_FLAG(x, bit) (!!((x)->flags & (bit)))
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/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
411 1. Smart Pannel 8-bit Bus Control Register.
598 #define CFG_BIAS_OUT(bias) ((bias)<<8) argument
685 /* FIXME - JUST GUESS */
811 /* read-only */
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/linux/drivers/net/ethernet/atheros/alx/
H A Dhw.c58 return -ETIMEDOUT; in alx_wait_mdio_idle()
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
208 spin_lock(&hw->mdio_lock); in alx_write_phy_ext()
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/linux/Documentation/admin-guide/
H A Dcgroup-v2.rst1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
22 1-1. Terminology
23 1-2. What is cgroup?
25 2-1. Mounting
26 2-2. Organizing Processes and Threads
27 2-2-1. Processes
28 2-2-2. Threads
29 2-3. [Un]populated Notification
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
96 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || in b43_nphy_ipa()
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); in b43_nphy_ipa()
101 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
112 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
137 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
143 u16 value, u8 core, bool off, in b43_nphy_rf_ctl_override_rev19() argument
149 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_main.c1 // SPDX-License-Identifier: GPL-2.0
33 static int debug = -1;
81 struct net_device *dev = adapter->netdev; in igc_reset()
82 struct igc_hw *hw = &adapter->hw; in igc_reset()
83 struct igc_fc_info *fc = &hw->fc; in igc_reset()
95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame in igc_reset()
97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); in igc_reset()
99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ in igc_reset()
100 fc->low_water = fc->high_water - 16; in igc_reset()
101 fc->pause_time = 0xFFFF; in igc_reset()
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