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Searched +full:bcm2835 +full:- +full:rng (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/rng/
H A Dbrcm,bcm2835.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/brcm,bcm2835.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835/6368 Random number generator
10 - Stefan Wahren <stefan.wahren@i2se.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Herbert Xu <herbert@gondor.apana.org.au>
17 - brcm,bcm2835-rng
18 - brcm,bcm-nsp-rng
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * bcm2835, bcm2836 and bcm2837 implementations.
8 interrupt-parent = <&intc>;
11 dma: dma-controller@7e007000 {
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-name
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H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_rng.c56 #define RNG_CTRL 0x00 /* RNG Control Register */
67 #define RNG_RBGEN_BIT 0x00000001 /* Enable RNG bit */
69 #define BCM2835_RNG_STATUS 0x04 /* BCM2835 RNG status register */
70 #define BCM2838_RNG_STATUS 0x18 /* BCM2838 RNG status register */
77 #define BCM2835_RND_VAL_WARM_CNT 0x40000 /* RNG Warm Up count */
78 #define BCM2835_RND_WARM_CNT 0xfffff /* RNG Warm Up Count mask */
80 #define BCM2835_RNG_DATA 0x08 /* RNG Data Register */
153 {"broadcom,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
154 {"brcm,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
156 {"brcm,bcm2711-rng200", (uintptr_t)&bcm2838_rng_conf},
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-i
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