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/linux/Documentation/devicetree/bindings/serial/
H A Dnvidia,tegra20-hsuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-hsuart
18 - nvidia,tegra30-hsuart
19 - nvidia,tegra186-hsuart
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H A Dserial-peripheral-props.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/serial-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial-attached Devices
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 controller, might need similar properties, e.g. for configuring the baud
16 rate.
19 max-speed:
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/linux/Documentation/devicetree/bindings/w1/
H A Dw1-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
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/linux/Documentation/misc-devices/
H A Doxsemi-tornado.rst1 .. SPDX-License-Identifier: GPL-2.0
10 The baud rate produced by the baud generator is obtained from this input
12 value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
14 value from 1 to 65535. Finally a programmable oversampling rate is used
16 determine the actual baud rate used. Baud rates from 15625000bps down
19 By default the oversampling rate is set to 16 and the clock prescaler is
21 for the usual 16-bit divisor is 115313.653, which is close enough to the
23 used for the divisor to obtain the requested baud rates by software that
26 The oversampling rate is programmed with the TCR register and the clock
38 obtained, with either exact or highly-accurate actual bit rates for
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/linux/drivers/tty/serial/
H A Dsuncore.c1 // SPDX-License-Identifier: GPL-2.0
32 drv->minor = sunserial_current_minor; in sunserial_register_minors()
33 drv->nr += count; in sunserial_register_minors()
35 if (drv->nr == count) in sunserial_register_minors()
39 drv->tty_driver->name_base = drv->minor - 64; in sunserial_register_minors()
47 drv->nr -= count; in sunserial_unregister_minors()
48 sunserial_current_minor -= count; in sunserial_unregister_minors()
50 if (drv->nr == 0) in sunserial_unregister_minors()
61 drv->cons = con; in sunserial_console_match()
78 con->index = line; in sunserial_console_match()
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H A Dserial-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
178 * RI - Ring detector is active in tegra_uart_get_mctrl()
179 * CD/DCD/CAR - Carrier detect is always active. For some reason in tegra_uart_get_mctrl()
181 * DSR - Data Set ready is active as the hardware doesn't support it. in tegra_uart_get_mctrl()
183 * CTS - Clear to send. Always set to active, as the hardware handles in tegra_uart_get_mctrl()
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H A Dvt8500_serial.c1 // SPDX-License-Identifier: GPL-2.0
33 #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
86 * Capability flags (driver-internal)
106 * have been allocated as we can't use pdev->id in
114 writel(val, port->membase + off); in vt8500_write()
119 return readl(port->membase + off); in vt8500_read()
128 vt8500_port->ier &= ~TX_FIFO_INTS; in vt8500_stop_tx()
129 vt8500_write(port, vt8500_port->ier, VT8500_URIER); in vt8500_stop_tx()
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H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
235 /* Read Register 2 (channel b only) - Interrupt vector */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
205 #define BRENABL 1 /* Baud rate generator enable */
206 #define BRSRC 2 /* Baud rate generator source */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define BRENAB 1 /* Baud rate generator enable */
189 #define BRSRC 2 /* Baud rate generator source */
239 /* Read Register 2 (channel b only) - Interrupt vector */
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H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
236 * These registers don't exist so we change the clk input rate in msm_serial_set_mnd_regs()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
244 else if (port->uartclk == 4800000) in msm_serial_set_mnd_regs()
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux/drivers/tty/
H A Dtty_baudrate.c1 // SPDX-License-Identifier: GPL-2.0
15 * Routine which returns the baud rate of the tty
50 * Convert termios baud rate data into a speed. This should be called
53 * ->c_[io]speed directly as they are updated.
62 cbaud = termios->c_cflag & CBAUD; in tty_termios_baud_rate()
66 return termios->c_ospeed; in tty_termios_baud_rate()
80 * Convert termios baud rate data into a speed. This should be called
83 * ->c_[io]speed directly as they are updated.
90 unsigned int cbaud = (termios->c_cflag >> IBSHIFT) & CBAUD; in tty_termios_input_baud_rate()
97 return termios->c_ispeed; in tty_termios_input_baud_rate()
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/linux/Documentation/w1/masters/
H A Dw1-uart.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …g a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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/linux/include/soc/fsl/qe/
H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
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/linux/drivers/media/rc/
H A Dite-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
98 /* duty cycle, 0-100 */
111 /* baud rate divisor default */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
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/linux/drivers/usb/serial/
H A Dkeyspan.c1 // SPDX-License-Identifier: GPL-2.0+
5 (C) Copyright (C) 2000-2001 Hugh Blemings <hugh@blemings.org>
6 (C) Copyright (C) 2002 Greg Kroah-Hartman <greg@kroah.com>
11 from Brian Warner's original Keyspan-PDA driver.
14 and Keyspan, Inc the manufacturers of the Keyspan USB-serial products.
79 /* Values used for baud rate calculation - device specific */
80 #define KEYSPAN_INVALID_BAUD_RATE (-1)
96 * usb-serial probe function.
100 /* Product IDs for the products supported, pre-renumeration */
115 * Product IDs post-renumeration. Note that the 28x and 28xb have the same
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H A Dpl2303.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2001-2007 Greg Kroah-Hartman (greg@kroah.com)
10 * See Documentation/usb/usb-serial.rst for more information on using this
248 struct device *dev = &serial->interface->dev; in pl2303_vendor_read()
252 if (spriv->type == &pl2303_type_data[TYPE_HXN]) in pl2303_vendor_read()
257 res = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0), in pl2303_vendor_read()
261 dev_err(dev, "%s - failed to read [%04x]: %d\n", __func__, in pl2303_vendor_read()
264 res = -EIO; in pl2303_vendor_read()
269 dev_dbg(dev, "%s - [%04x] = %02x\n", __func__, value, buf[0]); in pl2303_vendor_read()
277 struct device *dev = &serial->interface->dev; in pl2303_vendor_write()
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H A Dmct_u232.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
7 * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
8 * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
9 * Model No. U232-P9). See http://www.mct.com.tw/products/product_us232.html
11 * of this file. This device was used in the Dlink DSB-S25.
24 /* U232-P25, Sitecom */
27 /* DU-H3SP USB BAY hub */
28 #define MCT_U232_DU_H3SP_PID 0x0200 /* D-Link DU-H3SP USB BAY */
30 /* Belkin badge the MCT U232-P9 as the F5U109 */
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H A Dmos7720.c1 // SPDX-License-Identifier: GPL-2.0
14 * Greg Kroah-Hartman <gregkh@suse.de>
18 * Copyright (C) 2001-2002 Greg Kroah-Hartman <greg@kroah.com>
85 PPF = 2<<5, /* moschip calls this 'CB-FIFO mode */
97 atomic_t shadowDSR; /* updated in int-in callback */
186 struct usb_device *usbdev = serial->dev; in write_mos_reg()
195 dev_err(&usbdev->dev, in write_mos_reg()
208 struct usb_device *usbdev = serial->dev; in read_mos_reg()
220 return -ENOMEM; in read_mos_reg()
228 dev_err(&usbdev->dev, in read_mos_reg()
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/linux/drivers/tty/serial/8250/
H A D8250_mtk.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/dma-mapping.h>
28 #define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */
94 struct uart_8250_dma *dma = up->dma; in mtk8250_dma_rx_complete()
95 struct mtk8250_data *data = up->port.private_data; in mtk8250_dma_rx_complete()
96 struct tty_port *tty_port = &up->port.state->port; in mtk8250_dma_rx_complete()
102 if (data->rx_status == DMA_RX_SHUTDOWN) in mtk8250_dma_rx_complete()
105 uart_port_lock_irqsave(&up->port, &flags); in mtk8250_dma_rx_complete()
107 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); in mtk8250_dma_rx_complete()
108 total = dma->rx_size - state.residue; in mtk8250_dma_rx_complete()
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/linux/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * baycom_ser_fdx.c -- baycom ser12 fullduplex radio modem driver.
7 * Copyright (C) 1996-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
15 * ser12: This is a very simple 1200 baud AFSK modem. The modem consists only
24 * TXD pin of the serial port. Thus a contiguous stream of 0x00-bytes
27 * hsk: This is a 4800 baud FSK modem, designed for TNC use. It works fine
28 * in 'baycom-mode' :-) In contrast to the TCM3105 modem, power is
29 * externally supplied. So there's no need to provide the 0x00-byte-stream
37 * '#' denotes the baud rate / 100, eg. ser12* is '1200 baud, soft DCD'
39 * baud baud rate (between 300 and 4800)
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H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
150 #define BRENABL 1 /* Baud rate generator enable */
151 #define BRSRC 2 /* Baud rate generator source */
199 /* Read Register 2 (channel b only) - Interrupt vector */
217 /* Read Register 12 (lower byte of baud rate generator constant) */
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/linux/Documentation/ABI/testing/
H A Dsysfs-platform-kim11 firmware. The name exposed is read from the user-space
19 The maximum reliable baud-rate the host can support.
20 Different platforms tend to have different high-speed
21 UART configurations, so the baud-rate needs to be set
22 locally and also sent across to the WL128x via a HCI-VS
23 command. The entry is read and made use by the user-space
33 to have the capability of flow-control, or else this
43 transport driver, which will signal the user-space for opening,
44 configuring baud and install line discipline via this sysfs
45 entry. This entry would be polled upon by the user-space
/linux/Documentation/devicetree/bindings/sound/
H A Dserial-midi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/sound/serial-midi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Kaehn <kaehndan@gmail.com>
19 Can only be set to use standard baud rates corresponding to supported rates of the
20 parent serial device. If the standard MIDI baud of 31.25 kBaud is needed
22 configure the clocks of the parent serial device so that a requested baud of 38.4 kBaud
23 results in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default)
26 - $ref: /schemas/serial/serial-peripheral-props.yaml#
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