| /linux/fs/overlayfs/ |
| H A D | Kconfig | 22 "redirect_dir=off" module option or on a filesystem instance basis
53 "index=off" module option or on a filesystem instance basis with the
75 instance basis with the "nfs_export=off" mount option.
89 case basis with the "nfs_export=on" mount option.
120 module option or on a filesystem instance basis with the
|
| /linux/tools/testing/memblock/tests/ |
| H A D | common.c | 10 #define BASIS 10000 macro
79 * each node in basis point units (one hundredth of 1% or 1/10000).
95 assert(node_fracs[i] <= BASIS); in setup_numa_memblock()
96 phys_addr_t size = MEM_SIZE * node_fracs[i] / BASIS; in setup_numa_memblock()
|
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 43 …more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple …
52 … line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple …
61 … is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple …
|
| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 43 …more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple …
52 … line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple …
61 … is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple …
|
| /linux/tools/perf/pmu-events/arch/x86/clearwaterforest/ |
| H A D | cache.json | 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops. Note that L2 prefetcher requests that are dropped are not counted by this event. Counts on a per core basis.",
139 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
143 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
148 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
152 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.",
24 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
33 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
42 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
51 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
106 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
110 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
115 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
119 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
|
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | pipeline.json | 845 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
854 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
863 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
872 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
881 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
890 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
899 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
908 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
1027 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
1045 "PublicDescription": "This event counts, on the per-thread basis, cycle
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | pipeline.json | 845 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
854 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
863 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
872 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
881 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
890 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
899 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
908 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
1027 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
1045 "PublicDescription": "This event counts, on the per-thread basis, cycle
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | pipeline.json | 845 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
854 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
863 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
872 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
881 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
890 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
899 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
908 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
1027 "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
1045 "PublicDescription": "This event counts, on the per-thread basis, cycle
[all...] |
| /linux/include/net/ |
| H A D | tcp_ao.h | 132 * It needs SEQ basis to understand whereabouts are lower SEQ numbers.
133 * According to that basis vector, it can provide incremented SNE
136 * - for request sockets such basis is rcv_isn/snt_isn, which seems
138 * - for full sockets the basis is rcv_nxt/snd_una. snd_una is
142 * - for time-wait sockets the basis is tw_rcv_nxt/tw_snd_nxt.
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.",
24 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
33 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
42 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
51 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
106 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
110 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
115 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
119 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | cache.json | 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.",
19 "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
23 "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
27 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
31 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
36 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
40 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
45 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
49 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
54 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis
[all...] |
| /linux/Documentation/admin-guide/mm/ |
| H A D | zswap.rst | 26 Zswap evicts pages from compressed cache on an LRU basis to the backing swap
53 evict pages from its own compressed pool on an LRU basis and write them back to
118 zswap itself) on a cgroup-basis as follows::
|
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | cache.json | 16 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.",
145 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
164 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
193 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
212 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
278 "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.",
287 "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream that were throttled due to Demand Throttle Prefetcher. DTP Global Triggered with no Local Override. Counts on a per core basis.",
296 "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream and not throttled by DTP due to local override. These prefetches may still be throttled due to another throttler mechanism besides DTP. Counts on a per core basis.",
305 "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
546 "BriefDescription": "Counts the number of LLC prefetches that were throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | other.json | 16 …cles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
43 … unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
53 …elf (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
|
| H A D | cache.json | 7 …prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.",
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
58 … short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
63 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | other.json | 16 …cles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
43 … unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
53 …elf (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
|
| H A D | cache.json | 7 …prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.",
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
36 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
40 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.",
45 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
49 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.",
54 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
58 … short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
63 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
[all …]
|
| /linux/Documentation/scsi/ |
| H A D | aic79xx.rst | 283 per controller basis. Both controllers and targets
319 :Definition: Enable read streaming on a per target basis.
360 :Definition: Set Domain Validation Policy on a per-controller basis.
398 :Definition: Set IO Cell precompensation value on a per-controller basis.
421 :Definition: Set IO Cell slew rate on a per-controller basis.
444 :Definition: Set IO Cell signal amplitude on a per-controller basis.
|
| /linux/include/linux/ |
| H A D | ipc_namespace.h | 108 * basis instead of a per app basis. So, make the default high enough
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | pipeline.json | 675 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
684 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
693 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
702 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
711 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
720 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
729 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
738 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | pipeline.json | 685 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
694 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
703 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
712 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
721 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
730 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
739 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
748 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | pipeline.json | 685 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
694 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
703 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
712 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
721 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
730 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
739 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
748 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | cache.json | 219 "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.",
228 "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream that were throttled due to Demand Throttle Prefetcher. DTP Global Triggered with no Local Override. Counts on a per core basis.",
237 "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream and not throttled by DTP due to local override. These prefetches may still be throttled due to another throttler mechanism besides DTP. Counts on a per core basis.",
246 "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
451 "BriefDescription": "Counts the number of LLC prefetches that were throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.",
460 "BriefDescription": "Counts the number of LLC prefetches throttled due to Demand Throttle Prefetcher. DTP Global Triggered with no Local Override. Counts on a per core basis.",
469 "BriefDescription": "Counts the number of LLC prefetches not throttled by DTP due to local override. These prefetches may still be throttled due to another throttler mechanism. Counts on a per core basis.",
478 "BriefDescription": "Counts the number of LLC prefetches throttled due to LLC hit rate in <insert knob name here>. Counts on a per core basis.",
487 "BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
506 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis
[all...] |
| /linux/drivers/net/ |
| H A D | LICENSE.SRC | 14 on an "as-is" basis. No further updates to this software should be
|