| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | base.c | 52 /* Denies access to BAR2 when it's not initialised, used by INSTMEM in nvkm_bar_bar2_vmm()
56 if (bar && bar->bar2) in nvkm_bar_bar2_vmm()
57 return bar->func->bar2.vmm(bar); in nvkm_bar_bar2_vmm()
65 if (bar && bar->bar2) { in nvkm_bar_bar2_reset()
66 bar->func->bar2.init(bar); in nvkm_bar_bar2_reset()
67 bar->func->bar2.wait(bar); in nvkm_bar_bar2_reset()
75 if (bar && bar->bar2) { in nvkm_bar_bar2_fini()
76 bar->func->bar2.fini(bar); in nvkm_bar_bar2_fini()
77 bar->bar2 = false; in nvkm_bar_bar2_fini()
85 if (bar && bar->subdev.oneinit && !bar->bar2 && bar->func->bar2.init) { in nvkm_bar_bar2_init()
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| H A D | nv50.c | 91 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4); in nv50_bar_bar2_init()
128 /* BAR2 */ in nv50_bar_oneinit()
136 &bar2_lock, "bar2", &bar->bar2_vmm); in nv50_bar_oneinit()
151 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2); in nv50_bar_oneinit()
155 nvkm_kmap(bar->bar2); in nv50_bar_oneinit()
156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); in nv50_bar_oneinit()
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000); in nv50_bar_oneinit()
[all …]
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| H A D | gf100.c | 103 (bar_id == NVKM_BAR2_INST) ? "bar2" : "bar1", &bar_vm->vmm); in gf100_bar_oneinit_bar()
130 /* BAR2 */ in gf100_bar_oneinit()
131 if (bar->base.func->bar2.init) { in gf100_bar_oneinit()
184 .bar2.init = gf100_bar_bar2_init,
185 .bar2.fini = gf100_bar_bar2_fini,
186 .bar2.wait = gf100_bar_bar1_wait,
187 .bar2.vmm = gf100_bar_bar2_vmm,
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| H A D | gm107.c | 54 .bar2.init = gf100_bar_bar2_init,
55 .bar2.fini = gf100_bar_bar2_fini,
56 .bar2.wait = gm107_bar_bar2_wait,
57 .bar2.vmm = gf100_bar_bar2_vmm,
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| H A D | g84.c | 51 .bar2.init = nv50_bar_bar2_init,
52 .bar2.fini = nv50_bar_bar2_fini,
53 .bar2.wait = nv50_bar_bar1_wait,
54 .bar2.vmm = nv50_bar_bar2_vmm,
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| H A D | tu102.c | 88 .bar2.init = tu102_bar_bar2_init,
89 .bar2.fini = tu102_bar_bar2_fini,
90 .bar2.wait = tu102_bar_bar2_wait,
91 .bar2.vmm = gf100_bar_bar2_vmm,
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| H A D | nv50.h | 16 struct nvkm_gpuobj *bar2; member
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| H A D | priv.h | 23 } bar1, bar2; member
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/ |
| H A D | fbsr.c | 37 /* Restore BAR2 page tables via BAR0 window, and re-enable BAR2. */ in r570_fbsr_resume()
43 device->bar->bar2 = true; in r570_fbsr_resume()
48 /* Restore remaining BAR2 allocations (including BAR1 page tables) via BAR2. */ in r570_fbsr_resume()
107 /* Save BAR2 allocations to system memory. */ in r570_fbsr_suspend()
122 /* Disable BAR2 access. */ in r570_fbsr_suspend()
123 device->bar->bar2 = false; in r570_fbsr_suspend()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ |
| H A D | bar.c | 37 * BAR2 page tables have been restored. in r535_bar_flush()
39 if (unlikely(!bar->bar2)) { in r535_bar_flush()
112 bar->bar2 = true; in r535_bar_bar2_init()
181 rm->bar2.init = r535_bar_bar2_init; in r535_bar_new_()
182 rm->bar2.fini = r535_bar_bar2_fini; in r535_bar_new_()
183 rm->bar2.wait = r535_bar_bar2_wait; in r535_bar_new_()
184 rm->bar2.vmm = hw->bar2.vmm; in r535_bar_new_()
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | pci-octeon.h | 22 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
36 * For PCI (not PCIe) the BAR2 base address.
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| /linux/Documentation/translations/it_IT/doc-guide/ |
| H A D | parse-headers.rst | 165 enum foo { BAR1, BAR2, PRIVATE };
170 replace symbol BAR2 :c:type:\`foo\`
175 enum foo { BAR1, BAR2, PRIVATE };
177 Genererà un riferimento ai valori BAR1 e BAR2 dal simbolo foo nel dominio C.
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| /linux/drivers/net/ethernet/chelsio/cxgb4vf/ |
| H A D | t4vf_hw.c | 742 * t4vf_bar2_sge_qregs - return BAR2 SGE Queue register information
746 * @pbar2_qoffset: BAR2 Queue Offset
747 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
749 * Returns the BAR2 SGE Queue Registers information associated with the
754 * This may return an error which indicates that BAR2 SGE Queue
758 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
759 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
761 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
763 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
776 /* T4 doesn't support BAR2 SGE Queue registers. in t4vf_bar2_sge_qregs()
[all …]
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| H A D | adapter.h | 146 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
147 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
188 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
189 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
252 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
253 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
369 void __iomem *bar2; member
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| /linux/Documentation/translations/zh_CN/doc-guide/ |
| H A D | parse-headers.rst | 153 enum foo { BAR1, BAR2, PRIVATE };
158 replace symbol BAR2 :c:type:\`foo\`
163 enum foo { BAR1, BAR2, PRIVATE };
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | nvidia,tegra234-xusb.yaml | 26 - description: XUSB bar2 registers
32 - const: bar2
154 reg-names = "hcd", "fpci", "bar2";
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| /linux/drivers/mtd/maps/ |
| H A D | pci.c | 171 * We need to re-allocate PCI BAR2 address range to the in intel_dc21285_init()
172 * PCI ROM BAR, and disable PCI BAR2. in intel_dc21285_init()
206 * We need to undo the PCI BAR2/PCI ROM BAR address alteration. in intel_dc21285_exit()
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| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-function.rst | 241 BAR2 Peer Scratchpad
263 BAR2 Doorbell + Memory Window 1
281 | BAR2 | Local Memory | BAR2 |
309 | BAR2 | | Doorbell 3 +-------+ | +-----------------+
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| H A D | pci-vntb-function.rst | 110 BAR2 Memory Window 1
123 BAR2 Doorbell
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| /linux/Documentation/doc-guide/ |
| H A D | parse-headers.rst | 154 enum foo { BAR1, BAR2, PRIVATE };
164 replace symbol BAR2 :c:type:\`foo\`
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| /linux/arch/mips/cavium-octeon/ |
| H A D | dma-octeon.c | 93 /* Anything in the BAR1 hole or above goes via BAR2 */ in octeon_big_phys_to_dma()
121 /* Anything not in the BAR1 range goes via BAR2 */ in octeon_small_phys_to_dma()
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| H A D | memory.h | 33 u64 (*bar2)(struct nvkm_memory *); member
62 #define nvkm_memory_bar2(p) (p)->func->bar2(p)
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| /linux/drivers/uio/ |
| H A D | uio_mf624.c | 152 /* Note: Datasheet says device uses BAR0, BAR1, BAR2 -- do not trust it */ in mf624_pci_probe()
158 /* BAR2 */ in mf624_pci_probe()
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| /linux/include/linux/ |
| H A D | intel_dg_nvm_aux.h | 25 struct resource bar2; member
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| /linux/drivers/misc/bcm-vk/ |
| H A D | bcm_vk.h | 85 /* 64M mapped to BAR2 */
412 /* offset of the peer log control in BAR2 */
415 /* offset of processing monitoring info in BAR2 */
|