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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
13 device width times the number of interleaved chips.
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
H A Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
[all …]
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
20 kept in Hi-Z (tristate) after the start of a write access.
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
[all …]
H A Dintel,ixp4xx-flash.txt4 specific big-endian or mixed-endian memory access pattern.
7 - compatible : must be "intel,ixp4xx-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - bank-width : width in bytes of flash interface, should be <2>
11 For the rest of the properties, see mtd-physmap.txt.
13 The device tree may optionally contain sub-nodes describing partitions of the
19 compatible = "intel,ixp4xx-flash", "cfi-flash";
21 bank-width = <2>;
H A Dcortina,gemini-flash.txt7 - compatible : must be "cortina,gemini-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - syscon : must be a phandle to the system controller
10 - bank-width : width in bytes of flash interface, should be <2>
12 For the rest of the properties, see mtd-physmap.yaml.
14 The device tree may optionally contain sub-nodes describing partitions of the
20 compatible = "cortina,gemini-flash", "cfi-flash";
23 bank-width = <2>;
H A Darm-versatile.txt11 - compatible : must be "arm,versatile-flash", "cfi-flash";
12 - reg : memory address for the flash chip
13 - bank-width : width in bytes of flash interface.
15 For the rest of the properties, see mtd-physmap.txt.
17 The device tree may optionally contain sub-nodes describing partitions of the
23 compatible = "arm,versatile-flash", "cfi-flash";
25 bank-width = <4>;
H A Dorion-nand.txt4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
25 bank-width = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
H A Dpdm360ng.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009 - 2010 DENX Software Engineering.
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
27 bank-width = <0x1>;
41 compatible = "amd,s29gl01gp", "cfi-flash";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 bank-width = <4>;
[all …]
H A Dpcm032.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
5 * Copyright (C) 2006-2009 Pengutronix
11 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; };
14 &gpt4 { gpio-controller; };
15 &gpt5 { gpio-controller; };
16 &gpt6 { gpio-controller; };
17 &gpt7 { gpio-controller; };
[all …]
H A Dsbc8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
11 /dts-v1/;
13 /include/ "sbc8548-pre.dtsi"
17 #address-cells = <2>;
18 #size-cells = <1>;
19 compatible = "simple-bus";
21 interrupt-parent = <&mpic>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "intel,JS28F640", "cfi-flash";
[all …]
H A Dsbc8548-altflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 /dts-v1/;
16 /include/ "sbc8548-pre.dtsi"
20 #address-cells = <2>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
24 interrupt-parent = <&mpic>;
33 #address-cells = <1>;
34 #size-cells = <1>;
36 compatible = "intel,JS28F128", "cfi-flash";
[all …]
H A Dmgcoge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <16384>;
31 i-cache-size = <16384>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
[all …]
H A Dmc-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
13 to be defined in the peripheral node because they are per-peripheral
20 - Marek Vasut <marex@denx.de>
24 description: Bank number, base address and size of the device.
26 bank-width:
28 description: Bank width of the device, in bytes.
[all …]
/freebsd/sys/powerpc/mpc85xx/
H A Dlbc.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2006-2008, Juniper Networks, Inc.
133 * of 32KB - 4GB. Otherwise error code is returned. Value representing
153 return (0xffff8000 << (n - 15)); in lbc_address_mask()
163 if (sc->sc_range[r].size == 0) in lbc_banks_unmap()
166 pmap_unmapdev((void *)sc->sc_range[r].kva, in lbc_banks_unmap()
167 sc->sc_range[r].size); in lbc_banks_unmap()
168 law_disable(OCP85XX_TGTIF_LBC, sc->sc_range[r].addr, in lbc_banks_unmap()
169 sc->sc_range[r].size); in lbc_banks_unmap()
[all …]
H A Dlbc.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2008, Juniper Networks, Inc.
36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
90 vm_paddr_t addr; /* physical addr of the bank */
91 vm_size_t size; /* bank size */
92 vm_offset_t kva; /* VA of the bank */
95 * XXX the following bank attributes do not have properties specified
99 int width; /* data bus width */ member
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap-zoom-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
28 gpmc,device-width = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-gxl-s905x-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905x-cc", "amlogic,s905x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S905X-CC";
25 dio2133: analog-amplifier {
26 compatible = "simple-audio-amplifier";
[all …]

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