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/linux/drivers/bus/
H A Dbt1-axi.c8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
66 dev_crit_ratelimited(axi->dev, in bt1_axi_isr()
67 "AXI-bus fault %d: %s at 0x%x%08x\n", in bt1_axi_isr()
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/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
47 Optional properties for AXI DMA and MCDMA:
53 Optional properties for AXI DMA:
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/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
22 - xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
23 - xlnx,axi-str-rxd-tdata-width: Should be <0x20>
24 - xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
25 - xlnx,axi-str-txc-tdata-width: Should be <0x20>
26 - xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
27 - xlnx,axi-str-txd-tdata-width: Should be <0x20>
28 - xlnx,axis-tdest-width: AXI-Stream TDEST width (ignored by the driver)
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H A DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
12 to the AXI Ethernet without the need to use DMA.
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-axi-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
7 title: Allwinner A10 AXI Clock
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
44 axi@1c20054 {
46 compatible = "allwinner,sun4i-a10-axi-clk";
49 clock-output-names = "axi";
55 compatible = "allwinner,sun8i-a23-axi-clk";
58 clock-output-names = "axi";
H A Dbaikal,bt1-ccu-div.yaml26 3) AXI-bus clock dividers (AXI) - described in this binding file.
38 +----+ | | | +-|AXI|-|- AXI-bus
52 domain (like AXI-bus or System Device consumers). The dividers have the
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79 are called AXI-bus CCU. Both of them use the common clock bindings with no
82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
90 const: baikal,bt1-ccu-axi
125 - baikal,bt1-ccu-axi
154 # AXI-bus Clock Control Unit node:
159 compatible = "baikal,bt1-ccu-axi";
H A Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
30 clock is the AXI bus clock that needs to be enabled so we can access the
63 compatible = "adi,axi-clkgen-2.00.a";
/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
34 and length of the AXI DMA controller IO space, unless
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/linux/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-axi.yaml5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
8 title: Baikal-T1 AXI-bus
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
21 an IRQ is raised and a faulty situation is reported to the AXI EHB
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
31 const: baikal,bt1-axi
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
37 - description: AXI EHB MMIO system controller registers
87 compatible = "baikal,bt1-axi", "simple-bus";
H A Dbrcm,bus-axi.txt1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
9 The cores on the AXI bus are automatically detected by bcma with the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h3 * Definitions for Xilinx Axi Ethernet device driver.
73 /* Axi DMA Register definitions */
145 /* Axi Ethernet registers definition */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
209 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
229 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
233 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
237 /* Bit masks for Axi Ethernet RCW1 register */
253 /* Bit masks for Axi Ethernet TC register */
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/linux/Documentation/devicetree/bindings/sound/
H A Dadi,axi-spdif-tx.txt1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
7 The controller expects two clocks, the clock used for the AXI interface and
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
24 compatible = "adi,axi-spdif-tx-1.00.a";
27 clock-names = "axi", "ref";
H A Dadi,axi-i2s.txt1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
28 compatible = "adi,axi-i2s-1.00.a";
31 clock-names = "axi", "ref";
/linux/sound/soc/adi/
H A DMakefile2 snd-soc-adi-axi-i2s-y := axi-i2s.o
3 snd-soc-adi-axi-spdif-y := axi-spdif.o
5 obj-$(CONFIG_SND_SOC_ADI_AXI_I2S) += snd-soc-adi-axi-i2s.o
6 obj-$(CONFIG_SND_SOC_ADI_AXI_SPDIF) += snd-soc-adi-axi-spdif.o
H A DKconfig8 tristate "AXI-I2S support"
13 ASoC driver for the Analog Devices AXI-I2S softcore peripheral.
16 tristate "AXI-SPDIF support"
21 ASoC driver for the Analog Devices AXI-SPDIF softcore peripheral.
/linux/Documentation/devicetree/bindings/hwmon/
H A Dadi,axi-fan-control.yaml5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
8 title: Analog Devices AXI FAN Control
14 Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
22 - adi,axi-fan-control-1.00.a
51 fpga_axi: fpga-axi {
55 axi_fan_control: axi-fan-control@80000000 {
56 compatible = "adi,axi-fan-control-1.00.a";
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,pr-decoupler.yaml7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
23 eXchange AXI shutdown manager prevents AXI traffic from passing through the
26 preventing the system deadlock that can occur if AXI transactions are
38 - const: xlnx,dfx-axi-shutdown-manager-1.00
39 - const: xlnx,dfx-axi-shutdown-manager
/linux/Documentation/devicetree/bindings/dma/
H A Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
7 - clocks: Phandle and specifier to the controllers AXI interface clock
26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
43 compatible = "adi,axi-dmac-1.00.a";
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml145 - description: PCIe Master AXI clock
146 - description: PCIe Slave AXI clock
147 - description: PCIe Slave Q2A AXI clock
180 - description: PCIe Master AXI clock
181 - description: PCIe Slave AXI clock
182 - description: PCIe Slave Q2A AXI clock
185 - description: PCIe AGGRE NOC AXI clock
219 - description: PCIe Master AXI clock
220 - description: PCIe Slave AXI clock
221 - description: PCIe Slave Q2A AXI clock
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
124 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
130 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
134 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
148 /* MB AXI Target slaves */
155 /* MB AXI masters */
182 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dadi,axi-spi-engine.yaml4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
26 const: adi,axi-spi-engine-1.00.a
36 - description: The AXI interconnect clock.
56 compatible = "adi,axi-spi-engine-1.00.a";
/linux/Documentation/admin-guide/perf/
H A Dimx-ddr.rst17 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
49 This filter doesn't support filter different AXI ID for axid-read and axid-write
73 There is a limitation in previous AXI filter, it cannot filter different IDs
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_pci.c63 /* TODO: AXI */ in stmmac_default_data()
120 /* Axi Configuration */ in snps_gmac5_default_data()
121 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL); in snps_gmac5_default_data()
122 if (!plat->axi) in snps_gmac5_default_data()
125 plat->axi->axi_wr_osr_lmt = 31; in snps_gmac5_default_data()
126 plat->axi->axi_rd_osr_lmt = 31; in snps_gmac5_default_data()
128 plat->axi->axi_fb = false; in snps_gmac5_default_data()
129 plat->axi->axi_blen[0] = 4; in snps_gmac5_default_data()
130 plat->axi->axi_blen[1] = 8; in snps_gmac5_default_data()
131 plat->axi->axi_blen[2] = 16; in snps_gmac5_default_data()
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
33 when using the axi-xadc or the axi-system-management-wizard this must be
34 the clock that provides the clock to the AXI bus interface of the core.
110 compatible = "xlnx,axi-xadc-1.00.a";
/linux/Documentation/devicetree/bindings/usb/
H A Dstarfive,jh7110-usb.yaml42 - description: AXI clock
50 - const: axi
57 - description: AXI clock reset
64 - const: axi
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";

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