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/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stmpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
27 - st,stmpe1601
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
10 compatible = "fsl,imx28-evk", "fsl,imx28";
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
26 reg_vddio_sd0: regulator-vddio-sd0 {
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-phytec-segin-peb-av-02.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
9 backlight_lcd: backlight-lcd {
10 compatible = "pwm-backlight";
11 brightness-levels = <0 4 8 16 32 64 128 255>;
12 default-brightness-level = <5>;
13 power-supply = <&reg_backlight_en>;
18 lcd_panel: lcd-panel {
25 remote-endpoint = <&lcdif_parallel_out>;
30 reg_backlight_en: regulator-backlight-en {
31 compatible = "regulator-fixed";
[all …]
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
H A Dimx6ul-isiot.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
24 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
35 default-brightness-level = <100>;
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "1P8V";
[all …]
H A Dimx6qdl-phytec-mira.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "pwm-backlight";
15 brightness-levels = <0 4 8 16 32 64 128 255>;
16 default-brightness-level = <7>;
17 power-supply = <&reg_backlight>;
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpioleds>;
28 led-red {
29 label = "phyboard-mira:red";
[all …]
/linux/drivers/input/touchscreen/
H A Dmxs-lradc-ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/mfd/mxs-lradc.h>
25 "mxs-lradc-touchscreen",
26 "mxs-lradc-channel6",
27 "mxs-lradc-channel7",
93 return !!(readl(ts->base + LRADC_STATUS) & in mxs_lradc_check_touch_event()
101 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_map_ts_channel()
103 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_map_ts_channel()
117 LRADC_CH_NUM_SAMPLES(ts->over_sample_cnt - 1), in mxs_lradc_setup_ts_channel()
118 ts->base + LRADC_CH(ch)); in mxs_lradc_setup_ts_channel()
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H A Dbu21029_ts.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2018 Bosch Sicherheitssysteme GmbH
12 #include <linux/delay.h>
25 * +--------+--------+--------+--------+--------+--------+--------+--------+
27 * +--------+--------+--------+--------+--------+--------+--------+--------+
29 * +--------+--------+--------+--------+--------+--------+--------+--------+
31 * +--------+--------+--------+--------+--------+--------+--------+--------+
33 * +--------+--------+--------+--------+--------+--------+--------+--------+
35 * +--------+--------+--------+--------+--------+--------+--------+--------+
44 * +--------+--------+--------+--------+--------+--------+--------+--------+
[all …]
H A Dstmpe-ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/delay.h>
46 #define STMPE_TS_NAME "stmpe-ts"
50 * struct stmpe_touch - stmpe811 touch screen controller state
57 * (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
58 * @touch_det_delay: Touch detect interrupt delay
59 * (0 -> 10 us, 1 -> 50 us, 2 -> 100 us, 3 -> 500 us,
60 * 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms)
63 * (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 -> 1 ms,
64 * 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms)
[all …]
/linux/include/uapi/linux/spi/
H A Dspidev.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
6 * Andrea Paterniani <a.paterniani@swapp-eng.it>
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 * struct spi_ioc_transfer - describes a single SPI transfer
42 * @delay_usecs: If nonzero, how long to delay after the last bit transfer
52 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
53 * Zero-initialize the structure, including currently unused fields, to
65 * in a 16-bit word), the next could read a block of 8-bit data before
67 * could send a different nine bit command (re-selecting the chip), and the
94 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
/linux/include/clocksource/
H A Dtimer-ti-dm.h2 * OMAP Dual-Mode Timers
4 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/delay.h>
74 * These registers are offsets from timer->iobase.
90 * These registers are offsets from timer->func_base. The func_base
109 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
/linux/arch/arm/boot/dts/st/
H A Dstm32f429-disco.dts2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 /dts-v1/;
50 #include "stm32f429-pinctrl.dtsi"
51 #include <dt-bindings/input/input.h>
52 #include <dt-bindings/interrupt-controller/irq.h>
53 #include <dt-bindings/gpio/gpio.h>
56 model = "STMicroelectronics STM32F429i-DISCO board";
57 compatible = "st,stm32f429i-disco", "st,stm32f429";
[all …]
H A Dspear320-hmi.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear320-hmi", "st,spear320";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 st,pinmux-mode = <4>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
107 label = "u-boot";
129 compatible = "gpio-keys";
[all …]
H A Dspear1310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
63 smi-pmx {
127 label = "u-boot";
149 compatible = "gpio-keys";
[all …]
H A Dspear1340-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1340-evb", "st,spear1340";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
47 spdif-in {
51 spdif-out {
59 smi-pmx {
[all …]
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
[all …]
/linux/arch/mips/rb532/
H A Dirq.c20 * 675 Mass Ave, Cambridge, MA 02139, USA.
39 #include <linux/delay.h>
45 #include <asm/mach-rc32434/irq.h>
46 #include <asm/mach-rc32434/gpio.h>
83 return (irq_nr - GROUP0_IRQ_BASE) >> 5; in irq_to_group()
114 unsigned int group, intr_bit, irq_nr = d->irq; in rb532_enable_irq()
115 int ip = irq_nr - GROUP0_IRQ_BASE; in rb532_enable_irq()
123 ip &= (1 << 5) - 1; in rb532_enable_irq()
135 unsigned int group, intr_bit, mask, irq_nr = d->irq; in rb532_disable_irq()
136 int ip = irq_nr - GROUP0_IRQ_BASE; in rb532_disable_irq()
[all …]
/linux/drivers/net/ethernet/i825xx/
H A Dlasi_82596.c1 // SPDX-License-Identifier: GPL-1.0+
2 /* lasi_82596.c -- driver for the intel 82596 ethernet controller, as
9 3 primary sources of the mess --
27 03/02/2000 changes for better/correct(?) cache-flushing (deller)
34 This driver is for the Apricot 82596 bus-master interface
46 non-cached page, so we can run on 68060 in copyback mode.
53 Most of my modifications relate to the braindead big-endian
55 'big-endian' mode, it thinks a 32 bit value of 0x12345678
66 Scyld Computing Corporation, 410 Severn Ave., Suite 210, Annapolis MD 21403
77 #include <linux/delay.h>
[all …]
/linux/arch/arm/mach-omap1/
H A Dtime.c2 * linux/arch/arm/mach-omap1/time.c
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/delay.h>
77 return readl(&timer->read_tim); in omap_mpu_timer_read()
84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
105 writel(load_val, &timer->load_tim); in omap_mpu_timer_start()
107 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
[all …]
H A Dtimer32k.c2 * linux/arch/arm/mach-omap1/timer32k.c
6 * Copyright (C) 2004 - 2005 Nokia Corporation
10 * OMAP Dual-mode timer framework support by Timo Teras
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
39 #include <linux/delay.h>
58 * ---------------------------------------------------------------------------
66 * ---------------------------------------------------------------------------
79 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
129 .name = "32k-timer",
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h64-remix-mini-pc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64",
14 "allwinner,sun50i-a64";
22 stdout-path = "serial0:115200n8";
25 hdmi-connector {
26 compatible = "hdmi-connector";
[all …]
/linux/arch/arm/mach-omap2/
H A Dcommon.h22 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/delay.h>
33 #include <linux/platform_data/i2c-omap.h>
35 #include <linux/irqchip/irq-omap-intc.h>
37 #include <asm/proc-fns.h>
38 #include <asm/hardware/cache-l2x0.h>
183 /* This gets called from mach-omap2/io.c, do not call this */
196 * omap_test_timeout - busy-loop, testing a condition
/linux/Documentation/networking/device_drivers/ethernet/chelsio/
H A Dcxgb.rst1 .. SPDX-License-Identifier: GPL-2.0
35 Adaptive Interrupts (adaptive-rx)
36 ---------------------------------
46 By default, adaptive-rx is disabled.
47 To enable adaptive-rx::
49 ethtool -C <interface> adaptive-rx on
51 To disable adaptive-rx, use ethtool::
53 ethtool -C <interface> adaptive-rx off
55 After disabling adaptive-rx, the timer latency value will be set to 50us.
56 You may set the timer latency after disabling adaptive-rx::
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000_dma.h27 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/delay.h>
159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
176 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
185 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
197 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
201 if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) in halt_dma()
217 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
226 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; in dma_halted()
[all …]
/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
20 * Copyright (C) 2000-2001 Toshiba Corporation
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
50 #include <linux/delay.h>
64 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); in tx4927_pci_setup()
69 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) in tx4927_pci_setup()
77 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); in tx4927_pci_setup()
83 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); in tx4927_pci_setup()
95 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); in tx4927_pci_setup()
[all …]

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