| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-intel_pmt-features | 11 attributes describing the available telemetry, monitoring, or
31 - Lists available capabilities for this feature.
120 telemetry Available: No
121 watcher Available: Yes
122 crashlog Available: No
123 streaming Available: No
124 threashold Available: No
125 window Available: No
126 config Available: Yes
127 tracing Available: No
[all …]
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| H A D | debugfs-driver-genwqe | 10 Only available for PF.
16 Only available for PF.
22 Only available for PF.
28 Only available for PF.
35 Only available for PF.
41 Only available for PF.
47 Only available for PF.
53 Only available for PF.
73 The timeout depends on the max number of available cards
79 Only available for PF.
[all …]
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| /linux/Documentation/arch/powerpc/ |
| H A D | elf_hwcaps.rst | 13 Some hardware or software features are only available on some CPU
15 discovery mechanism available to userspace code. The kernel exposes the
50 whether this class is available to be used, but the specifics depend on the
51 ISA version. For example, if the VSX facility is available, the VSX
84 Vector (aka Altivec, VMX) facility is available.
87 Floating point facility is available.
102 Signal Processing Engine facility is available.
105 Embedded Floating Point single precision operations are available.
108 Embedded Floating Point double precision operations are available.
111 The timebase facility (mftb instruction) is not available.
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | memory.json | 16 …n": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: …
26 …": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: …
37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: …
48 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: …
59 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: …
70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: …
81 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: …
92 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: …
103 …fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: …
114 …L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: …
[all …]
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| H A D | cache.json | 164 …"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST cou…
175 …s required and modified data was forwarded from another core or module. Available PDIST counters: …
186 … "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: …
197 …"Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: …
208 …ion": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: …
219 …on": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: …
230 …ion": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: …
241 … a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: …
252 … "PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0",
263 … "PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | memory.json | 16 …n": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: …
26 …": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: …
37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: …
48 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: …
59 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: …
70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: …
81 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: …
92 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: …
103 …fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: …
114 …L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: …
[all …]
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| H A D | cache.json | 164 …"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST cou…
175 …s required and modified data was forwarded from another core or module. Available PDIST counters: …
186 … "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: …
197 …"Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: …
208 …ion": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: …
219 …on": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: …
230 …ion": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: …
241 … a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: …
252 … "PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0",
263 … "PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0",
[all …]
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| /linux/Documentation/hwmon/ |
| H A D | it87.rst | 12 Datasheet: Not publicly available
26 Datasheet: Not publicly available
34 Datasheet: Once publicly available at the ITE website, but no longer
42 Datasheet: Once publicly available at the ITE website, but no longer
50 Datasheet: Once publicly available at the ITE website, but no longer
58 Datasheet: Once publicly available at the ITE website, but no longer
66 Datasheet: Not publicly available
74 Datasheet: Not publicly available
82 Datasheet: Not publicly available
90 Datasheet: Not publicly available
[all …]
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | commonring.c | 70 u16 available; in brcmf_commonring_write_available() local
75 available = commonring->depth - commonring->w_ptr + in brcmf_commonring_write_available()
78 available = commonring->r_ptr - commonring->w_ptr; in brcmf_commonring_write_available()
80 if (available > 1) { in brcmf_commonring_write_available()
83 if (available > commonring->depth / 8) { in brcmf_commonring_write_available()
111 u16 available; in brcmf_commonring_reserve_for_write() local
116 available = commonring->depth - commonring->w_ptr + in brcmf_commonring_reserve_for_write()
119 available = commonring->r_ptr - commonring->w_ptr; in brcmf_commonring_reserve_for_write()
121 if (available > 1) { in brcmf_commonring_reserve_for_write()
147 u16 available; in brcmf_commonring_reserve_for_write_multiple() local
[all …]
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| /linux/tools/include/uapi/linux/ |
| H A D | kvm.h | 315 /* Available with KVM_CAP_INTERNAL_ERROR_DATA: */
692 * Check if a kvm extension is available. Argument is extension number,
1032 * Available with KVM_CAP_IRQFD_RESAMPLE
1081 /* Available with KVM_CAP_ONE_REG */
1142 * Device control API, available with KVM_CAP_DEVICE_CTRL
1252 /* Available with KVM_CAP_PIT_STATE2 */
1255 /* Available with KVM_CAP_PPC_GET_PVINFO */
1257 /* Available with KVM_CAP_TSC_CONTROL for a vCPU, or with
1261 /* Available with KVM_CAP_SIGNAL_MSI */
1263 /* Available with KVM_CAP_PPC_GET_SMMU_INFO */
[all …]
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| /linux/include/uapi/linux/ |
| H A D | kvm.h | 315 /* Available with KVM_CAP_INTERNAL_ERROR_DATA: */
692 * Check if a kvm extension is available. Argument is extension number,
1033 * Available with KVM_CAP_IRQFD_RESAMPLE
1082 /* Available with KVM_CAP_ONE_REG */
1143 * Device control API, available with KVM_CAP_DEVICE_CTRL
1253 /* Available with KVM_CAP_PIT_STATE2 */
1256 /* Available with KVM_CAP_PPC_GET_PVINFO */
1258 /* Available with KVM_CAP_TSC_CONTROL for a vCPU, or with
1262 /* Available with KVM_CAP_SIGNAL_MSI */
1264 /* Available with KVM_CAP_PPC_GET_SMMU_INFO */
[all …]
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| /linux/drivers/pci/hotplug/ |
| H A D | cpqphp_nvram.c | 188 u32 available; in load_HRT() local
196 available = 1024; in load_HRT()
199 temp_dword = available; in load_HRT()
226 u32 available; in store_HRT() local
236 available = 1024; in store_HRT()
254 rc = add_byte(&pFill, 1 + ctrl->push_flag, &usedbytes, &available); in store_HRT()
259 rc = add_byte(&pFill, 1, &usedbytes, &available); in store_HRT()
269 rc = add_byte(&pFill, ctrl->bus, &usedbytes, &available); in store_HRT()
274 rc = add_byte(&pFill, PCI_SLOT(ctrl->pci_dev->devfn), &usedbytes, &available); in store_HRT()
279 rc = add_byte(&pFill, PCI_FUNC(ctrl->pci_dev->devfn), &usedbytes, &available); in store_HRT()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/clearwaterforest/ |
| H A D | cache.json | 25 "PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1",
34 … "PublicDescription": "Counts the number of store ops retired. Available PDIST counters: 0,1",
45 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
56 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
67 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
78 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
89 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
100 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
111 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
122 …efined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: …
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | cache.json | 323 …SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: …
333 "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
343 …"PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST c…
353 …"PublicDescription": "Counts retired load instructions with locked access. Available PDIST counter…
366 …ounts retired load instructions that split across a cacheline boundary. Available PDIST counters: …
379 …unts retired store instructions that split across a cacheline boundary. Available PDIST counters: …
392 …retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: …
405 …ber of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: …
418 …ired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
428 …red store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
[all …]
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| H A D | memory.json | 75 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
87 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
99 …6 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
111 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
123 …6 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
135 …2 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
147 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
159 …2 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
171 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
183 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | cache.json | 392 …ts Instructions with at least one architecturally visible load retired. Available PDIST counters: …
403 "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0,1",
413 …"PublicDescription": "Counts all retired software prefetch instructions. Available PDIST counters:…
424 …"PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST c…
435 …"PublicDescription": "Counts retired load instructions with locked access. Available PDIST counter…
446 …ounts retired load instructions that split across a cacheline boundary. Available PDIST counters: …
457 …unts retired store instructions that split across a cacheline boundary. Available PDIST counters: …
468 …r of retired instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: …
479 …retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: …
490 …ber of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: …
[all …]
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| H A D | memory.json | 38 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
51 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
64 …6 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
77 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
90 …6 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
103 …2 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
116 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
129 …2 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
142 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
155 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: …
[all …]
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| H A D | pipeline.json | 48 … successfully retires. All branch type instructions are accounted for. Available PDIST counters: …
57 … "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0,1",
66 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0,…
76 …Counts the number of not taken conditional branch instructions retired. Available PDIST counters: …
86 …"PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0,1",
96 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte…
106 …ption": "Counts taken backward conditional branch instructions retired. Available PDIST counters: …
116 …iption": "Counts taken forward conditional branch instructions retired. Available PDIST counters: …
126 … "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0,1",
136 …t is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] Available PDIST counters: …
[all …]
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| /linux/drivers/hv/ |
| H A D | hv_trace_balloon.h | 10 TP_PROTO(u64 available, u64 committed,
15 TP_ARGS(available, committed, vm_memory_committed,
18 __field(u64, available)
26 __entry->available = available;
33 TP_printk("available %lld, committed %lld; vm_memory_committed %ld;"
35 __entry->available, __entry->committed,
|
| /linux/fs/ubifs/ |
| H A D | budget.c | 109 * as not available);
178 * The index head is not available for the in-the-gaps method, so add an in ubifs_calc_min_idx_lebs()
188 * ubifs_calc_available - calculate available FS space.
192 * This function calculates and returns amount of FS space available for use.
197 long long available; in ubifs_calc_available() local
199 available = c->main_bytes - c->lst.total_used; in ubifs_calc_available()
202 * Now 'available' contains theoretically available flash space in ubifs_calc_available()
220 available -= (long long)subtract_lebs * c->leb_size; in ubifs_calc_available()
222 /* Subtract the dead space which is not available for use */ in ubifs_calc_available()
223 available -= c->lst.total_dead; in ubifs_calc_available()
[all …]
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| /linux/drivers/media/dvb-frontends/ |
| H A D | as102_fe_types.h | 24 /* constellation available values */
30 /* hierarchy available values */
37 /* interleaving available values */
42 /* code rate available values */
50 /* guard interval available values */
57 /* transmission mode available values */
63 /* DVBH signalling available values */
67 /* tune state available */
76 /* available TS FID filter types */
81 /* number of echos available */
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | cache.json | 377 …SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: …
387 "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
397 …"PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST c…
407 …"PublicDescription": "Counts retired load instructions with locked access. Available PDIST counter…
417 …ounts retired load instructions that split across a cacheline boundary. Available PDIST counters: …
427 …unts retired store instructions that split across a cacheline boundary. Available PDIST counters: …
437 …ired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
447 …red store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
466 …oad instructions whose data sources were HitM responses from shared L3. Available PDIST counters: …
476 …a sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: …
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | cache.json | 377 …SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: …
387 "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
397 …"PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST c…
407 …"PublicDescription": "Counts retired load instructions with locked access. Available PDIST counter…
417 …ounts retired load instructions that split across a cacheline boundary. Available PDIST counters: …
427 …unts retired store instructions that split across a cacheline boundary. Available PDIST counters: …
437 …ired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
447 …red store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: …
466 …oad instructions whose data sources were HitM responses from shared L3. Available PDIST counters: …
476 …a sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: …
[all …]
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| /linux/Documentation/i2c/busses/ |
| H A D | i2c-viapro.rst | 7 Datasheet: Sometimes available at the VIA website
10 Datasheet: Sometimes available at the VIA website
13 Datasheet: available on request from VIA
16 Datasheet: available on request and under NDA from VIA
19 Datasheet: available on request and under NDA from VIA
22 Datasheet: available on http://linux.via.com.tw
25 Datasheet: available on http://linux.via.com.tw
28 Datasheet: available on http://linux.via.com.tw
|
| /linux/kernel/irq/ |
| H A D | matrix.c | 12 unsigned int available; member
91 cm->available = m->alloc_size; in irq_matrix_online()
92 cm->available -= cm->managed + m->systembits_inalloc; in irq_matrix_online()
95 m->global_available += cm->available; in irq_matrix_online()
109 /* Update the global available size */ in irq_matrix_offline()
110 m->global_available -= cm->available; in irq_matrix_offline()
146 if (!cm->online || cm->available <= maxavl) in matrix_find_best_cpu()
150 maxavl = cm->available; in matrix_find_best_cpu()
229 cm->available--; in irq_matrix_reserve_managed()
279 cm->available++; in irq_matrix_remove_managed()
[all …]
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