available (full) in projects: linux - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched full:available (Results 1 – 25 of 4936) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...198

/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	pipeline.json	9 …iption": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: … 19 …re root operations. Accounts for integer and floating-point operations. Available PDIST counters: … 30 …tion": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: … 40 …"PublicDescription": "This event counts the cycles the integer divider is busy. Available PDIST co… 51 …ption": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: … 60 …e. Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: … 69 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0", 77 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0", 86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0", 95 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte… [all …]
H A D	cache.json	7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0", 16 …, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: … 25 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 36 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 46 …: "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: … 55 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 64 …line splits and reads due to page walks resulted from any request type. Available PDIST counters: … 74 …"PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters:… 83 …mber of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: … 92 …hose lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: … [all …]
H A D	frontend.json	7 … the branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: … 16 …cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: … 25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0", 34 … counts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: … 45 …ced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: … 56 … means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: … 67 …retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: … 78 …ts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: … 89 …ts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: … 100 …riod of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: … [all …]
H A D	virtual-memory.json	7 …oads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: … 17 …one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: … 26 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 35 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 44 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 53 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 62 …utstanding for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: … 71 … stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: … 81 …least one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: … 90 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	pipeline.json	9 …iption": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: … 19 …re root operations. Accounts for integer and floating-point operations. Available PDIST counters: … 30 …tion": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: … 40 …"PublicDescription": "This event counts the cycles the integer divider is busy. Available PDIST co… 51 …ption": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: … 60 …e. Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: … 69 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0", 77 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0", 86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0", 95 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte… [all …]
H A D	cache.json	7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0", 16 …, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: … 25 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 36 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 46 …: "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: … 55 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 64 …line splits and reads due to page walks resulted from any request type. Available PDIST counters: … 74 …"PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters:… 83 …mber of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: … 92 …hose lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: … [all …]
H A D	frontend.json	7 … the branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: … 16 …cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: … 25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0", 34 … counts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: … 45 …ced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: … 56 … means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: … 67 …retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: … 78 …ts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: … 89 …ts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: … 100 …riod of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: … [all …]
H A D	virtual-memory.json	7 …oads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: … 17 …one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: … 26 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 35 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 44 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 53 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 62 …utstanding for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: … 71 … stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: … 81 …least one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: … 90 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	pipeline.json	8 …re root operations. Accounts for integer and floating-point operations. Available PDIST counters: … 18 …"PublicDescription": "This event counts the cycles the integer divider is busy. Available PDIST co… 27 …e. Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: … 36 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0", 44 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0", 53 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0", 62 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte… 71 "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0", 80 …nstructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: … 89 …tion": "Counts both direct and indirect near call instructions retired. Available PDIST counters: … [all …]
H A D	cache.json	7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0", 16 …, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: … 25 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 36 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 45 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 54 …line splits and reads due to page walks resulted from any request type. Available PDIST counters: … 64 …"PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters:… 73 …mber of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: … 82 …hose lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: … 91 …lines are typically in Shared or Exclusive state. A non-threaded event. Available PDIST counters: … [all …]
H A D	memory.json	8 …"PublicDescription": "Cycles while L3 cache miss demand load is outstanding. Available PDIST count… 18 …ion": "Execution stalls while L3 cache miss demand load is outstanding. Available PDIST counters: … 27 …ad may not conform to the memory ordering rules of the x86 architecture Available PDIST counters: … 37 …"PublicDescription": "Cycles while L1 cache miss demand load is outstanding. Available PDIST count… 47 …ion": "Execution stalls while L1 cache miss demand load is outstanding. Available PDIST counters: … 57 …tanding (will not count for uncacheable demand requests e.g. bus lock). Available PDIST counters: … 67 …tanding (will not count for uncacheable demand requests e.g. bus lock). Available PDIST counters: … 79 …4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: … 91 …8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: … 103 …6 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: … [all …]
H A D	frontend.json	7 … the branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: … 16 …cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: … 25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0", 34 … counts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: … 45 … (ANT) conditional retired branches (no BTB entry and not mispredicted) Available PDIST counters: … 56 …ced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: … 70 … means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: … 81 …retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: … 95 …ts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: … 109 …ts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: … [all …]
H A D	virtual-memory.json	7 …oads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: … 17 …one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: … 26 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 35 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 44 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 53 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … 62 …utstanding for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: … 71 … stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: … 81 …least one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: … 90 …d further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: … [all …]
/linux/Documentation/ABI/testing/
H A D	sysfs-class-intel_pmt-features	`11 attributes describing the available telemetry, monitoring, or 31 - Lists available capabilities for this feature. 120 telemetry Available: No 121 watcher Available: Yes 122 crashlog Available: No 123 streaming Available: No 124 threashold Available: No 125 window Available: No 126 config Available: Yes 127 tracing Available: No [all …]`
/linux/Documentation/hwmon/
H A D	isl68137.rst	14 Publicly available at the Renesas website 25 Publicly available (after August 2020 launch) at the Renesas website 35 Publicly available (after August 2020 launch) at the Renesas website 45 Publicly available (after August 2020 launch) at the Renesas website 55 Publicly available (after August 2020 launch) at the Renesas website 65 Publicly available (after August 2020 launch) at the Renesas website 75 Publicly available (after August 2020 launch) at the Renesas website 85 Publicly available (after August 2020 launch) at the Renesas website 95 Publicly available (after August 2020 launch) at the Renesas website 105 Publicly available (after August 2020 launch) at the Renesas website [all …]
/linux/Documentation/arch/powerpc/
H A D	elf_hwcaps.rst	13 Some hardware or software features are only available on some CPU 15 discovery mechanism available to userspace code. The kernel exposes the 50 whether this class is available to be used, but the specifics depend on the 51 ISA version. For example, if the VSX facility is available, the VSX 84 Vector (aka Altivec, VMX) facility is available. 87 Floating point facility is available. 102 Signal Processing Engine facility is available. 105 Embedded Floating Point single precision operations are available. 108 Embedded Floating Point double precision operations are available. 111 The timebase facility (mftb instruction) is not available. [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	memory.json	16 …n": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: … 26 …": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: … 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 48 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: … 59 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: … 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 81 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: … 92 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: … 103 …fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: … 114 …L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: … [all …]
H A D	cache.json	164 …"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST cou… 175 …s required and modified data was forwarded from another core or module. Available PDIST counters: … 186 … "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: … 197 …"Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: … 208 …ion": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: … 219 …on": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: … 230 …ion": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: … 241 … a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: … 252 … "PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0", 263 … "PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0", [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	memory.json	16 …n": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: … 26 …": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: … 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 48 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: … 59 …iption": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: … 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 81 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: … 92 …acks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: … 103 …fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: … 114 …L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: … [all …]
H A D	cache.json	164 …"PublicDescription": "Counts the number of load uops retired that hit in DRAM. Available PDIST cou… 175 …s required and modified data was forwarded from another core or module. Available PDIST counters: … 186 … "Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: … 197 …"Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: … 208 …ion": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: … 219 …on": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: … 230 …ion": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: … 241 … a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: … 252 … "PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0", 263 … "PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0", [all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	pipeline.json	18 …re root operations. Accounts for integer and floating-point operations. Available PDIST counters: … 29 …"PublicDescription": "This event counts the cycles the integer divider is busy. Available PDIST co… 39 …e. Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: … 58 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0", 76 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0", 86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0", 105 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte… 124 "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0", 143 …nstructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: … 190 …tion": "Counts both direct and indirect near call instructions retired. Available PDIST counters: … [all …]
H A D	cache.json	17 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0", 27 …, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: … 37 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 49 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 59 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 69 …line splits and reads due to page walks resulted from any request type. Available PDIST counters: … 80 …"PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters:… 90 …mber of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: … 150 …hose lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: … 170 …lines are typically in Shared or Exclusive state. A non-threaded event. Available PDIST counters: … [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	pipeline.json	9 …iption": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: … 30 …re root operations. Accounts for integer and floating-point operations. Available PDIST counters: … 60 …tion": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: … 81 …"PublicDescription": "This event counts the cycles the integer divider is busy. Available PDIST co… 111 …ption": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: … 121 …e. Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: … 140 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0", 168 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0", 178 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0", 197 …"PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counte… [all …]
H A D	cache.json	7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0", 17 …, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: … 27 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 39 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 50 …: "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: … 60 …cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: … 70 …line splits and reads due to page walks resulted from any request type. Available PDIST counters: … 81 …"PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters:… 91 …mber of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: … 101 …hose lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: … [all …]
H A D	frontend.json	17 … the branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: … 27 …cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: … 37 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0", 47 … counts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: … 59 …ced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: … 71 … means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: … 83 …retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: … 95 …ts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: … 107 …ts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: … 119 …riod of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: … [all …]

12 3 4 5 6 7 8 9 10 >>...198