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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,wcd939x-usbss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,wcd939x-usbss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm WCD9380/WCD9385 USB SubSystem Altmode/Analog Audio Switch
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 Qualcomm WCD9390/WCD9395 is a standalone Hi-Fi audio codec IC with a
14 functionally separate USB SubSystem for Altmode/Analog Audio Switch
16 The Audio Headphone and Microphone data path between the Codec and the
17 USB-C Mux subsystems are external to the IC, thus requiring DT port-endpoint
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dclk-s5pv210-audss.txt1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and compatible SoCs.
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
[all …]
H A Dclk-exynos-audss.txt1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
9 - compatible: should be one of the following:
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13 - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
15 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
17 - reg: physical base address and length of the controller's register set.
19 - #clock-cells: should be 1.
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H A Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
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H A Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
25 - marvell,mmp2-audio-clock
32 - description: Audio subsystem clock
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H A Damlogic,axg-audio-clkc.txt1 * Amlogic AXG Audio Clock Controllers
3 The Amlogic AXG audio clock controller generates and supplies clock to the
4 other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
9 - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
10 "amlogic,g12a-audio-clkc" for G12A,
11 "amlogic,sm1-audio-clkc" for S905X3.
12 - reg : physical base address of the clock controller and length of
14 - clocks : a list of phandle + clock-specifier pairs for the clocks listed
15 in clock-names.
16 - clock-names : must contain the following:
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H A Damlogic,axg-audio-clkc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG Audio Clock Controller
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
14 The Amlogic AXG audio clock controller generates and supplies clock to the
15 other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
21 - amlogic,axg-audio-clkc
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/freebsd/sys/contrib/device-tree/Bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
12 standard. The subsystem includes multiple functional blocks as below:
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dsamsung,exynos5433-lpass.txt1 Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
5 - compatible : "samsung,exynos5433-lpass"
6 - reg : should contain the LPASS top SFR region location
8 - clock-names : should contain following required clocks: "sfr0_ctrl"
9 - clocks : should contain clock specifiers of all clocks, which
10 input names have been specified in clock-names
12 - #address-cells : should be 1
13 - #size-cells : should be 1
14 - ranges : must be present
16 Each IP block of the Low Power Audio Subsystem should be specified as
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H A Dsamsung,exynos5433-lpass.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpas
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dsprd-mcdt.txt1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
4 transmission between audio subsystem and other AP/CP subsystem. It
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
H A Duniphier,aio.txt1 Socionext UniPhier SoC audio driver
3 The Socionext UniPhier audio subsystem consists of I2S and S/PDIF blocks in
7 - compatible : should be one of the following:
8 "socionext,uniphier-ld11-aio"
9 "socionext,uniphier-ld20-aio"
10 "socionext,uniphier-pxs2-aio"
11 - reg : offset and length of the register set for the device.
12 - interrupts : should contain I2S or S/PDIF interrupt.
13 - pinctrl-names : should be "default".
14 - pinctrl-0 : defined I2S signal pins for an external codec chip.
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H A Dqcom,q6apm-lpass-dais.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6apm-lpass-dais.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm DSP LPASS (Low Power Audio SubSystem) Audio Ports
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: dai-common.yaml#
19 - qcom,q6apm-lpass-dais
21 '#sound-dai-cells':
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H A Dmt2701-afe-pcm.txt4 - compatible: should be one of the following.
5 - "mediatek,mt2701-audio"
6 - "mediatek,mt7622-audio"
7 - interrupts: should contain AFE and ASYS interrupts
8 - interrupt-name
[all...]
H A Dqcom,wcd939x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm WCD9380/WCD9385 Audio Codec
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
15 The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem
17 The Audio Headphone and Microphone data path between the Codec and the USB-C Mux
18 subsystems are external to the IC, thus requiring DT port-endpoint graph description
19 to handle USB-C altmode & orientation switching for Audio Accessory Mode.
[all …]
H A Dfsl,aud2htx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Audio Subsystem to HDMI RTX Subsystem Controller
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 const: fsl,imx8mp-aud2htx
24 - description: Peripheral clock
26 clock-names:
28 - const: bus
32 - description: DMA controller phandle and request line for TX
[all …]
H A Dqcom,q6dsp-lpass-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 This binding describes the Qualcomm DSP LPASS Audio ports
18 - qcom,q6afe-dais
20 '#sound-dai-cells':
23 '#address-cells':
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroidxu3-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3 audio subsystem device tree source
11 #include <dt-bindings/sound/samsung-i2s.h>
15 compatible = "samsung,odroid-xu3-audio";
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,sm4250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Audio voting clock
[all …]
H A Dqcom,lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
19 const: qcom,sm8250-lpass-lpi-pinctrl
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
30 clock-names:
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H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpas
[all...]
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpas
[all...]
H A Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpas
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dnvidia,tegra210-aconnect.txt4 components inside the Audio Processing Engine (APE). All CPU accesses to
5 the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
8 - compatible: Must be "nvidia,tegra210-aconnect".
9 - clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
11 - clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
13 - power-domains: Must contain a phandle that points to the audio powergate
15 - #address-cells: The number of cells used to represent physical base addresses
17 - #size-cells: The number of cells used to represent the size of an address
19 - ranges: Mapping of the aconnect address space to the CPU address space.
21 All devices accessed via the ACONNNECT are described by child-nodes.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Dpx30-ringneck-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "px30-ringneck.dtsi"
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
13 compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
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