Searched full:aud_pll_div1_lpcg (Results 1 – 5 of 5) sorted by relevance
21 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,51 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,244 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
130 <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,457 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,605 aud_pll_div1_lpcg: clock-controller@59d30000 { label659 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
38 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
679 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;691 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
871 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;883 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;