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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nominal.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
19 assigned-clock-rates = <0>, <0>,
24 fsl,operating-mode = "nominal";
28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
30 assigned-clock-rates = <800000000>;
34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
H A Dimx8mm-overdrive.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/reset/imx8mp-reset-audiomix.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interconnect/fsl,imx8mp.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dimx8mn-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/usb/pd.h>
11 stdout-path = &uart2;
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
22 default-state = "on";
26 hdmi-connector {
27 compatible = "hdmi-connector";
[all …]
H A Dimx8-ss-lvds1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
H A Dimx8mm-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
14 stdout-path = &uart2;
22 hdmi-connector {
23 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
[all …]
H A Dimx8mq-mnt-reform2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright 2019-2021 MNT Research GmbH
8 /dts-v1/;
10 #include "imx8mq-nitrogen-som.dtsi"
14 compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15 chassis-type = "laptop";
18 compatible = "pwm-backlight";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_backlight>;
22 power-supply = <&reg_main_usb>;
[all …]
H A Dimx8qxp-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
9 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
15 bt_sco_codec: audio-codec-bt {
16 compatible = "linux,bt-sco";
17 #sound-dai-cells = <1>;
21 stdout-path = &lpuart0;
24 imx8x_cm4: imx8x-cm4 {
25 compatible = "fsl,imx8qxp-cm4";
[all …]
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
[all …]
/linux/drivers/clk/
H A Dclk-conf.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
21 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
22 "#clock-cells"); in __set_clk_parents()
23 if (num_parents == -EINVAL) in __set_clk_parents()
24 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
28 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
29 "#clock-cells", index, &clkspec); in __set_clk_parents()
32 if (rc == -ENOENT) in __set_clk_parents()
[all …]
H A Dkunit_clk_assigned_rates_one_consumer.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 clk: kunit-clock {
9 compatible = "test,clk-assigned-rates";
10 #clock-cells = <0>;
13 kunit-clock-consumer {
14 compatible = "test,clk-consumer";
15 assigned-clocks = <&clk>;
16 assigned-clock-rates = <ASSIGNED_RATES_0_RATE>;
/linux/Documentation/devicetree/bindings/phy/
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
16 "clk_ade_core" for the ADE core clock.
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,imx8qxp-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cai Huoqing <caihuoqing@baidu.com>
17 const: nxp,imx8qxp-adc
28 clock-names:
30 - const: per
31 - const: ipg
33 assigned-clocks:
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 additional standard clock DT bindings required for Tegra.
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
[all …]
H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
H A Dbrcm,cygnus-audio.txt4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
H A Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
21 - $ref: dai-common.yaml#
25 pattern: "^dspk@[0-9a-f]*$"
[all …]
H A Dnvidia,tegra210-dmic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
24 pattern: "^dmic@[0-9a-f]*$"
28 - const: nvidia,tegra210-dmic
29 - items:
[all …]
H A Dnvidia,tegra210-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Inter-IC Sound (I2S) controller implements full-duplex,
11 bi-directional and single direction point-to-point serial
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
24 pattern: "^i2s@[0-9a-f]*$"
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-zii-rpu2.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * RPU - Remote Peripheral Unit
10 /dts-v1/;
11 #include <dt-bindings/thermal/thermal.h>
16 compatible = "zii,imx7d-rpu2", "fsl,imx7d";
19 stdout-path = &uart2;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
28 cs2000_in_dummy: dummy-oscillator {
[all …]

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