aspm\-pwr\-on\-t\-us (full) in projects: freebsd

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Searched +full:aspm +full:- +full:pwr +full:- +full:on +full:- +full:t +full:- +full:us (Results 1 – 8 of 8) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A D	nvidia,tegra194-pcie-ep.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode. [all …]
H A D	nvidia,tegra194-pcie.txt	3 This PCIe controller is based on the Synopsis Designware PCIe IP 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and 5 snps,dw-pcie-ep.yaml. 10 - power-domains: A phandle to the node that controls power to the respective 20 "include/dt-bindings/power/tegra194-powergate.h" file. 21 - reg: A list of physical base address and length pairs for each set of 22 controller registers. Must contain an entry for each entry in the reg-names 24 - reg-names: Must include the following entries: 26 "config": As per the definition in snps,dw-pcie.yaml 32 - interrupts: A list of interrupt outputs of the controller. Must contain an [all …]
H A D	nvidia,tegra194-pcie.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device [all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A D	tegra234.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gi [all...]`
H A D	tegra194.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra194-clock.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gi [all...]`
/freebsd/sys/dev/wpi/
H A D	if_wpi.c	1 /- 24 The 3945ABG network adapter doesn't use traditional hardware as 27 * main binary firmware image into SRAM on the card via DMA. 37 * the firmware updates the read index (reg1) on rx of a packet and fires an 55 * on the majority of communications between the driver and the card goes 317 for (ident = wpi_ident_table; ident->name != NULL; ident++) { in wpi_probe() 318 if (pci_get_vendor(dev) == ident->vendor && in wpi_probe() 319 pci_get_device(dev) == ident->device) { in wpi_probe() 320 device_set_desc(dev, ident->name); in wpi_probe() 339 sc->sc_dev = dev; in wpi_attach() [all …]
/freebsd/sys/dev/iwn/
H A D	if_iwn.c	1 /- 2 Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 90 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, [all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 95 …on the PCIE adapter. This value can be written by firmware through the PCIE private register space… 116 … (0x1<<9) // Fast back-to-back transaction ena… [all …]