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17 * The exception fixup information "just so happens" to be arranged
269 * subtracted out. This is arranged so that folks manipulating ISA
19 arranged in vertical stripe.
40 slot for this processor has been loaded. We've arranged
28 are always arranged in memory from left to right, and from top to
30 The second plane provides 16-bit per-pixel Depth data arranged in
19 * Keep this list arranged in rough order of priority. Anything listed after
34 * arranged as shown below:
154 * arranged as shown below:211 * arranged as shown below:248 * Control-bits are arranged as shown below:278 * They are arranged as shown below:
74 packets of data arranged back to back. It can be done as follows:
9 * This test creates that scenario: three CPUs are arranged in a ring. The BPF
45 /* The fetch and add registers are allocated here. They are arranged
66 * remote node index so the table is arranged in sets of three. The bits are
56 Extents are arranged as a tree. Each node of the tree begins with a
97 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
31 * are arranged for flexibility. We convert the table data to host native
86 /* Flat array, arranged in groups */
46 /* 16-bit c_can registers can be arranged differently in the memory
119 systems. In such systems the memory is arranged into banks that have
63 The bits of the ioport are arranged as follows:
148 /* FIFO data are arranged in chunks of 64bits */ in axg_tdmout_prepare()
134 strobe) input, arranged so that the data input bits appear as contiguous
71 parse expressions, but we do want whitespace to be arranged