Searched +full:armada +full:- +full:3700 +full:- +full:uart +full:- +full:clock (Results 1 – 9 of 9) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/serial/ |
H A D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs 2 e.g., Armada-3700. 5 - compatible: 6 - "marvell,armada-3700-uart" for the standard variant of the UART 7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the 9 - "marvell,armada-3700-uart-ext" for the extended variant of the 10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit 12 - reg: offset and length of the register set for the device. 13 - clocks: UART reference clock used to derive the baudrate. If no clock 14 is provided (possible only with the "marvell,armada-3700-uart" [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
H A D | armada-37xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 model = "Marvell Armada 37xx SoC"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 25 reserved-memory { 26 #address-cells = <2>; [all …]
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H A D | ac5-98dx25xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <2>; 21 #size-cells = <0>; 23 cpu-map { 36 compatible = "arm,cortex-a55"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | marvell,armada-3700-uart-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 title: Marvell Armada 3720 UART clocks 9 - Pali Rohár <pali@kernel.org> 13 const: marvell,armada-3700-uart-clock 17 - description: UART Clock Control Register 18 - description: UART 2 Baud Rate Divisor Register 22 List of parent clocks suitable for UART from following set: [all …]
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/freebsd/sys/arm64/conf/ |
H A D | std.marvell | 9 device a37x0_gpio # Marvell Armada 37x0 GPIO controller 14 device a37x0_iic # Armada 37x0 I2C controller 23 # Real-time clock support 24 device mv_rtc # Marvell Real-time Clock 27 device safexcel # Inside Secure EIP-97 33 device a37x0_spi # Marvell Armada 37x0 SPI Controller 36 device uart_mvebu # Armada 3700 UART driver 37 device uart_ns8250 # ns8250-type UART driver 41 device neta # Marvell Armada 370/38x/XP/3700 NIC 58 device a37x0_xtal # Marvell xtal-clock [all …]
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H A D | NOTES | 2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs. 25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols 30 options VFP # Floating-point support 64 device qcom_gcc # Global Clock Controller 69 # Microsoft Hyper-V 80 device al_pci # Annapurna Alpine PCI-E 81 options PCI_HP # PCI-Express native HotPlug 82 options PCI_IOV # PCI SR-IOV support 88 device neta # Marvell Armada 370/38x/XP/3700 NIC 102 # Broadcom MPT Fusion, version 4, is 64-bit only [all …]
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/freebsd/sys/dev/uart/ |
H A D | uart_dev_mvebu.c | 1 /*- 37 #include <dev/uart/uart.h> 38 #include <dev/uart/uart_bus.h> 39 #include <dev/uart/uart_cpu.h> 40 #include <dev/uart/uart_cpu_fdt.h> 61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */ 62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */ 93 #define UART_CCR 0x10 /* Clock Control Register */ 127 * Low-level UART interface. 174 /* Reset UART */ in uart_mvebu_param() [all …]
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/freebsd/sys/contrib/device-tree/src/arm/marvell/ |
H A D | armada-385-synology-ds116.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 /dts-v1/; 9 #include "armada-385.dtsi" 10 #include <dt-bindings/gpio/gpio.h> 14 compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; 17 stdout-path = "serial0:115200n8"; 32 internal-reg [all...] |
/freebsd/share/misc/ |
H A D | pci_vendors | 5 # Date: 2025-03-09 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 41 7a09 PCI-to-PCI Bridge 51 7a19 PCI-to-PCI Bridge 57 7a29 PCI-to-PCI Bridge [all …]
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