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Searched +full:armada +full:- +full:370 +full:- +full:corediv +full:- +full:clock (Results 1 – 6 of 6) sorted by relevance

/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-98dx3236.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
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H A Darmada-370-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * This file contains the definitions that are common to the Armada
13 * 370 and Armada XP SoC.
19 model = "Marvell Armada 370 and XP SoC";
20 compatible = "marvell,armada-370-xp";
28 #address-cells = <1>;
29 #size-cells = <0>;
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H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 375 family SoC
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 375 family SoC";
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H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 39x family of SoCs.
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
31 #address-cells = <1>;
32 #size-cells = <0>;
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H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 38x family SoC";
32 compatible = "arm,cortex-a9-pmu";
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/linux/drivers/clk/mvebu/
H A Dclk-corediv.c1 // SPDX-License-Identifier: GPL-2.0
3 * MVEBU Core divider clock
7 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 #include <linux/clk-provider.h>
23 * to configure one particular core divider clock. Those hardware
37 * array of core divider clock descriptors for this SoC, as well as
50 * This structure represents one core divider clock for the clock
51 * framework, and is dynamically allocated for each core divider clock
70 { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
74 { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
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