| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,realview.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM RealView Boards
10 - Linus Walleij <linus.walleij@linaro.org>
13 The ARM RealView series of reference designs were built to explore the Arm11,
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
[all …]
|
| H A D | apple.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/apple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple ARM Machine
10 - Hector Martin <marcan@marcan.st>
13 ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
17 - Mac mini (M1, 2020)
18 - MacBook Pro (13-inch, M1, 2020)
19 - MacBook Air (M1, 2020)
[all …]
|
| H A D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/ar
[all...] |
| H A D | arm,integrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/ar
[all...] |
| H A D | arm,scmi.txt | 2 ----------------------------------------------------------
5 that are provided by the hardware platform it is running on, including power
9 the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
10 and Management Interface Platform Design Document")[0] provide for OSPM in
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
[all …]
|
| H A D | vexpress-scc.txt | 1 ARM Versatile Express Serial Configuration Controller
2 -----------------------------------------------------
4 Test chips for ARM Versatile Express platform implement SCC (Serial
11 like platform configuration control and power management.
15 - compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
18 eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
19 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
23 - reg: when the SCC is memory mapped, physical address and size of the
25 - interrupts: when the SCC can generate a system-level interrupt
30 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
|
| H A D | vexpress-sysreg.txt | 1 ARM Versatile Express system registers
2 --------------------------------------
5 platform functions like board detection and identification, software
9 - compatible value : = "arm,vexpress,sysreg";
10 - reg : physical base address and the size of the registers window
13 - gpio-controller : specifies that the node is a GPIO controller
14 - #gpio-cells : size of the GPIO specifier, should be 2:
15 - first cell is the pseudo-GPIO line number:
16 0 - MMC CARDIN
17 1 - MMC WPROT
[all …]
|
| H A D | arm,corstone1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Corstone1000
10 - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11 - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
[all …]
|
| H A D | arm,versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/ar
[all...] |
| /freebsd/sys/conf/ |
| H A D | files.arm | 2 arm/arm/autoconf.c standard
3 arm/arm/bcopy_page.S standard
4 arm/arm/bcopyinout.S standard
5 arm/arm/blockio.S standard
6 arm/arm/bus_space_asm_generic.S standard
7 arm/arm/bus_space_base.c optional fdt
8 arm/arm/bus_space_generic.c standard
9 arm/arm/busdma_machdep.c standard
10 arm/arm/copystr.S standard
11 arm/arm/cpufunc.c standard
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | arm,scmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2021 ARM Ltd.
4 ---
5 $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
15 that are provided by the hardware platform it is running on, including power
19 the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
20 and Management Interface Platform Design Document")[0] provide for OSPM in
23 [0] https://developer.arm.com/documentation/den0056/latest
[all …]
|
| /freebsd/crypto/openssl/ |
| H A D | NOTES-ANDROID.md | 5 -------------------
15 -------------
17 Android is a cross-compiled target and you can't rely on `./Configure`
19 target explicitly; there are `android-arm`, `android-arm64`, `android-mips`,
20 `android-mip64`, `android-x86` and `android-x86_64` (`*MIPS` targets are no
23 Do not pass --cross-compile-prefix (as you might be tempted), as it
24 will be "calculated" automatically based on chosen platform. However,
30 to point at the `NDK` directory. If you're using a side-by-side NDK the path
31 will look something like `/some/where/android-sdk/ndk/<ver>`, and for a
32 standalone NDK the path will be something like `/some/where/android-ndk-<ver>`.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/ |
| H A D | qman.txt | 3 Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
7 - QMan Node
8 - QMan Private Memory Nodes
9 - Example
13 The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
16 flow-level queuing, is also responsible for congestion management functions such
22 - compatible
26 May include "fsl,<SoC>-qman"
28 - reg
30 Value type: <prop-encoded-array>
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM MHUv2 Mailbox Controller
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
33 - Data-transfer: Each transfer is made of one or more words, using one or more
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | arm,integrator-ap-lm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
12 description: The Integrator/AP is a prototyping platform and as such has a
14 use with this platform. A special system controller register can be read to
17 then have their own specific per-module bindings and they will be described
21 "#address-cells":
24 "#size-cells":
[all …]
|
| /freebsd/share/man/man7/ |
| H A D | arch.7 | 1 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
40 For full details consult the processor-specific ABI supplement
86 .Bl -column -offset indent "Architecture" "Initial Release"
100 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
103 .It arm Ta 6.0 Ta 12.4
128 .Bl -tag -width "Dv ILP32"
133 types machine representations all have 4-byte size.
147 Typically these are 64-bit machines, where the
153 environment, which was the historical 32-bit predecessor for 64-bit evolution.
[all …]
|
| /freebsd/sys/arm/arm/ |
| H A D | pl310.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
45 #ifdef PLATFORM
53 #ifdef PLATFORM
60 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/DDI0246E_l2c310_r3p1_trm.pdf
65 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246b/pr01s02s02.html
72 mtx_lock_spin(&(sc)->sc_mtx); \
76 mtx_unlock_spin(&(sc)->sc_mtx); \
85 static const uint32_t g_l2cache_align_mask = (32 - 1);
94 {"arm,pl310", true}, /* Non-standard, FreeBSD. */
[all …]
|
| H A D | mpcore_timer.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
35 * The ARM Cortex-A9 core can support a global timer plus a private and
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
69 #include <arm/arm/mpcore_timervar.h>
71 /* Private (per-CPU) timer register map */
114 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
115 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/opp/ |
| H A D | opp.txt | 2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 operating-points = <
39 Binding 2: operating-points-v2
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/arm/ |
| H A D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
29 * (HBI0182 + HBI0183) as described in ARM DUI 0440B
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
32 arm,hbi = <0x182>;
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
[all …]
|
| /freebsd/usr.sbin/bsdinstall/scripts/ |
| H A D | bootconfig | 2 #-
53 --title "$DIALOG_TITLE" \
54 --backtitle "$DIALOG_BACKTITLE" \
55 --hline "$hline" \
56 --ok-label "Ok" \
57 --no-cancel \
58 --inputbox "$prompt" \
65 nentries=$(efibootmgr | grep -c "${EFI_LABEL_NAME}$")
67 if [ ${nentries} -eq 0 ]; then
69 …efibootmgr --create --activate --label "$EFI_LABEL_NAME" --loader "${mntpt}/${FREEBSD_BOOTNAME}" >…
[all …]
|
| /freebsd/crypto/openssl/Configurations/ |
| H A D | 50-win-onecore.conf | 1 ## -*- mode: perl; -*-
17 …my $SDKver = `powershell -Command \"& {\$(Get-Item \\\"hklm:\\SOFTWARE\\WOW6432Node\\Microsoft\\M…
25 $UWP_info->{disable} = [ 'asm' ];
27 $UWP_info->{disable} = [ ];
34 "VC-WIN32-ONECORE" => {
35 inherit_from => [ "VC-WIN32" ],
39 # /APPCONTAINER is needed for Universal Windows Platform compat
44 "VC-WIN64A-ONECORE" => {
45 inherit_from => [ "VC-WIN64A" ],
51 # Windows on ARM targets. ARM compilers are additional components in
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | arm,mps2-timer.txt | 1 ARM MPS2 timer
3 The MPS2 platform has simple general-purpose 32 bits timers.
6 - compatible : Should be "arm,mps2-timer"
7 - reg : Address and length of the register set
8 - interrupts : Reference to the timer interrupt
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM MPS2 timer
16 timer1: mps2-timer@40000000 {
17 compatible = "arm,mps2-timer";
23 timer2: mps2-timer@40001000 {
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/arm/ |
| H A D | juno-motherboard.dtsi | 2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
11 mb_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
18 mb_clk25mhz: clock-25000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
|
| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_sdma.h | 1 /*-
27 #define SDMAARM_MC0PTR 0x00 /* ARM platform Channel 0 Pointer */
33 #define SDMAARM_HOSTOVR 0x18 /* Channel ARM platform Override */
37 #define SDMAARM_INTRMASK 0x2C /* Channel ARM platform Interrupt Mask */
52 #define SDMAARM_XTRIG_CONF1 0x70 /* Cross-Trigger Events Configuration Register 1 */
53 #define SDMAARM_XTRIG_CONF2 0x74 /* Cross-Trigger Events Configuration Register 2 */
|