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Searched +full:archs +full:- +full:intc (Results 1 – 14 of 14) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arc/
H A Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Dvdk_axc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 * HS38x2 (Dual Core) with IDU intc (VDK version)
15 #address-cells = <1>;
16 #size-cells = <1>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <50000000>;
[all …]
H A Daxc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Dhaps_hs_idu.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
10 model = "snps,zebu_hs-smp";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
22 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 compatible = "simple-bus";
31 #address-cells = <1>;
[all …]
H A Dnsimosci_hs_idu.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
10 model = "snps,nsimosci_hs-smp";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
18 …n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
26 compatible = "simple-bus";
27 #address-cells = <1>;
[all …]
H A Dvdk_axc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 #address-cells = <1>;
15 #size-cells = <1>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <50000000>;
30 core_intc: archs-intc@cpu {
[all …]
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
H A Dnsimosci_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
20 …8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
H A Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsnps,archs-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS incore Interrupt Controller
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA.
14 intc accessed via the special ARC AUX register interface, hence "reg" property
19 const: snps,archs-intc
21 interrupt-controller: true
[all …]
H A Dsnps,archs-idu-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS Interrupt Distribution Unit
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
15 load balancing of common/external IRQs towards core intc.
22 const: snps,archs-idu-intc
24 interrupt-controller: true
[all …]
H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
5 intc.
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
H A Dsnps,archs-intc.txt1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
5 - compatible: "snps,archs-intc"
6 - interrupt-controller: This is an interrupt controller.
7 - #interrupt-cells: Must be <1>.
12 intc accessed via the special ARC AUX register interface, hence "reg" property
17 intc: interrupt-controller {
18 compatible = "snps,archs-intc";
19 interrupt-controller;
20 #interrupt-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,arc-timer.txt2 - Found on all ARC CPUs (ARC700/ARCHS)
3 - Can be optionally programmed to interrupt on Limit
4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
10 - compatible : should be "snps,arc-timer"
11 - interrupts : single Interrupt going into parent intc
12 (16 for ARCHS cores, 3 for ARC700 cores)
13 - clock
[all...]