| /linux/Documentation/arch/powerpc/ |
| H A D | isa-versions.rst | 10 CPU Architecture version
24 Power5 - PowerPC User Instruction Set Architecture Book I v2.02
25 - PowerPC Virtual Environment Architecture Book II v2.02
26 - PowerPC Operating Environment Architecture Book III v2.02
27 PPC970 - PowerPC User Instruction Set Architecture Book I v2.01
28 - PowerPC Virtual Environment Architecture Book II v2.01
29 - PowerPC Operating Environment Architecture Book III v2.01
31 Power4+ - PowerPC User Instruction Set Architecture Book I v2.01
32 - PowerPC Virtual Environment Architecture Book II v2.01
33 - PowerPC Operating Environment Architecture Book III v2.01
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| H A D | elf_hwcaps.rst | 67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
131 The processor implements the embedded category ("BookE") architecture.
147 The processor supports the v2.05 userlevel architecture. Processors
160 The processor supports the v2.06 userlevel architecture. Processors
182 The processor supports the v2.07 userlevel architecture. Processors
209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
228 The processor supports the v3.1 userlevel architecture. Processors
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| /linux/include/linux/ |
| H A D | entry-common.h | 19 * Define dummy _TIF work flags if not defined by the architecture or for
72 * arch_enter_from_user_mode - Architecture specific sanity check for user mode regs
75 * Defaults to an empty implementation. Can be replaced by architecture
98 * Invoked from architecture specific syscall entry code with interrupts
103 * This is invoked when there is architecture specific functionality to be
125 * Invoked from architecture specific syscall entry code with interrupts
133 * This is invoked when there is extra architecture specific functionality
147 * Invoked from architecture specific syscall entry code with interrupts
149 * architecture specific work.
180 * Invoked from architecture specific syscall entry code with interrupts
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| /linux/drivers/perf/arm_cspmu/ |
| H A D | Kconfig | 6 tristate "ARM Coresight Architecture PMU"
10 based on ARM CoreSight PMU architecture. Note that this PMU
11 architecture does not have relationship with the ARM CoreSight
15 tristate "NVIDIA Coresight Architecture PMU"
19 (PMU) devices based on ARM CoreSight PMU architecture.
22 tristate "Ampere Coresight Architecture PMU"
26 (PMU) devices based on ARM CoreSight PMU architecture.
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| /linux/arch/sparc/crypto/ |
| H A D | Kconfig | 17 Architecture: sparc64
27 Architecture: sparc64 using crypto instructions, when available
37 Architecture: sparc64
47 Architecture: sparc64 using crypto instructions, when available
57 Architecture: sparc64 using crypto instructions, when available
67 Architecture: sparc64 using crypto instructions
78 Architecture: sparc64
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| /linux/Documentation/mm/ |
| H A D | memory-model.rst | 16 FLATMEM and SPARSEMEM. Each architecture defines what
43 To allocate the `mem_map` array, architecture specific setup code should
48 An architecture may free parts of the `mem_map` array that do not cover the
49 actual physical pages. In such case, the architecture specific
75 `MAX_PHYSMEM_BITS` constants defined by each architecture that
77 physical address that an architecture supports, the
100 The architecture setup code should call sparse_init() to
119 To use vmemmap, an architecture has to reserve a range of virtual
122 the architecture should implement :c:func:`vmemmap_populate` method
124 virtual memory map. If an architecture does not have any special
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | hypercalls.rst | 45 2. Architecture(s)
52 :Architecture: x86
60 :Architecture: x86
68 :Architecture: PPC
79 :Architecture: PPC
89 :Architecture: x86
105 :Architecture: x86
143 :Architecture: x86
164 :Architecture: x86
175 :Architecture: x86
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| /linux/scripts/package/ |
| H A D | mkdebian | 27 # Attempt to find the correct Debian architecture
84 debarch=$(dpkg-architecture -qDEB_HOST_ARCH)
88 echo "Your architecture doesn't have its equivalent" >&2
89 echo "Debian userspace architecture defined!" >&2
90 echo "Falling back to the current host architecture ($debarch)." >&2
192 host_gnu=$(dpkg-architecture -a "${debarch}" -q DEB_HOST_GNU_TYPE | sed 's/_/-/g')
219 Architecture: $debarch
231 Architecture: $debarch
242 Architecture: $debarch
257 Architecture
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| /linux/tools/perf/pmu-events/ |
| H A D | README | 19 - To reduce JSON event duplication per architecture, platform JSONs may
20 use "ArchStdEvent" keyword to dereference an "Architecture standard
21 events", defined in architecture standard JSONs.
22 Architecture standard JSONs must be located in the architecture root
44 - Set of 'PMU events tables' for all known CPUs in the architecture,
61 - A 'mapping table' that maps each CPU of the architecture, to its
86 3. _All_ known CPU tables for architecture are included in the perf
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | cpus.txt | 2 Power Architecture CPU Binding
5 Power Architecture CPUs in Freescale SOCs are represented in device trees as
17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some architecture categories not defined
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| /linux/Documentation/features/ |
| H A D | arch-support.txt | 2 For generic kernel features that need architecture support, the
8 | ok | # feature supported by the architecture
9 |TODO| # feature not yet supported by the architecture
11 | N/A| # feature doesn't apply to the architecture
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| /linux/Documentation/core-api/irq/ |
| H A D | irqflags-tracing.rst | 15 CONFIG_PROVE_RWSEM_LOCKING will be offered on an architecture - these
19 Architecture support for this is certainly not in the "trivial"
21 state changes. But an architecture can be irq-flags-tracing enabled in a
42 - if the architecture has non-maskable interrupts then those need to be
47 implementation in an architecture: lockdep will detect that and will
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| /linux/include/asm-generic/ |
| H A D | tlb.h | 116 * And allows the architecture to provide and implement tlb_flush():
134 * If an architecture does not provide tlb_flush() a default implementation
145 * This might be useful if your architecture has size specific TLB
153 * Useful if your architecture has non-page page directories.
155 * When used, an architecture is expected to provide __tlb_remove_table() or
164 * Useful if your architecture doesn't use IPIs for remote TLB invalidates
169 * Indicates the architecture has flush_cache_range() but it needs *NOT* be called
178 * Indicates the architecture wants to merge ranges over VMAs; typical when
183 * Use this if your architecture lacks an efficient flush_tlb_range(). This
193 * This is useful if your architecture already flushes TLB entries in the
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| H A D | ticket_spinlock.h | 7 * guarantees under contention. If your architecture cannot provide this, stick
12 * you'd be hard pressed to find anything useful in architecture specifications
13 * about this. If your architecture cannot do this you might be better off with
22 * architecture has WFE like instructions to sleep instead of poll for word
94 * Remapping spinlock architecture specific functions to the corresponding
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| /linux/Documentation/timers/ |
| H A D | highres.rst | 48 code out of the architecture-specific areas into a generic management
49 framework, as illustrated in figure #3 (OLS slides p. 18). The architecture
76 for various event driven functionalities is hardwired into the architecture
80 architecture. Another implication of the current design is that it is necessary
81 to touch all the architecture-specific implementations in order to provide new
87 to minimize the clock event related architecture dependent code to the pure
93 Clock event devices are registered either by the architecture dependent boot
116 architecture specific timer interrupt handlers and hands the control over the
131 The conversion of an architecture has no functional impact, but allows to
135 adding the kernel/time/Kconfig file to the architecture specific Kconfig and
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| /linux/drivers/infiniband/ulp/srpt/ |
| H A D | ib_dm_mad.h | 45 * InfiniBand Architecture Specification.
55 * Architecture Specification.
87 * Architecture Specification.
98 * the InfiniBand Architecture Specification.
132 * See also section 16.3.3.5 ServiceEntries in the InfiniBand Architecture
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| /linux/drivers/clk/bcm/ |
| H A D | Kconfig | 30 based on the ARM architecture
38 based on the MIPS architecture
47 based on the MIPS architecture.
62 based on the iProc architecture
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| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fred.rst | 10 The FRED architecture defines simple new transitions that change
11 privilege level (ring transitions). The FRED architecture was
23 The new transitions defined by the FRED architecture are FRED event
31 In addition to these transitions, the FRED architecture defines a new
36 Furthermore, the FRED architecture is easy to extend for future CPU
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| /linux/tools/memory-model/Documentation/ |
| H A D | references.txt | 9 o SPARC International Inc. (Ed.). 1994. "The SPARC Architecture
12 o Compaq Computer Corporation (Ed.). 2002. "Alpha Architecture
44 o ARM Ltd. (Ed.). 2014. "ARM Architecture Reference Manual (ARMv8,
45 for ARMv8-A architecture profile)". ARM Ltd.
47 o Imagination Technologies, LTD. 2015. "MIPS(R) Architecture
54 Sewell. 2016. "Modelling the ARMv8 Architecture, Operationally:
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| /linux/lib/crypto/ |
| H A D | Kconfig | 31 Declares whether the architecture provides an arch-specific
47 Declares whether the architecture provides an arch-specific
77 Declares whether the architecture provides an arch-specific
117 Declares whether the architecture provides an arch-specific
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| /linux/tools/power/cpupower/man/ |
| H A D | cpupower-idle-info.1 | 33 processor. This often is the case on the X86 architecture when the acpi_idle
39 state residencies. Please refer to the architecture specific description
42 .SH IDLE\-INFO ARCHITECTURE SPECIFIC DESCRIPTIONS
53 There exist two different cpuidle drivers on the X86 architecture platform:
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | realtek,usb2phy.yaml | 20 The USB architecture includes three XHCI controllers.
30 The USB architecture includes two XHCI controllers.
38 The USB architecture includes three XHCI controllers.
46 The USB architecture includes three XHCI controllers.
54 The USB architecture includes three XHCI controllers.
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| /linux/arch/mips/jazz/ |
| H A D | Kconfig | 9 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
20 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
30 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
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| /linux/Documentation/core-api/ |
| H A D | genericirq.rst | 22 interrupt subsystem based for their architecture, with the help of the
67 Analysing a couple of architecture's IRQ subsystem implementations
81 and extensible. For example, an (sub)architecture can use a generic
83 (sub)architecture specific 'edge type' implementation.
118 Whenever an interrupt triggers, the low-level architecture code calls
173 The interrupt flow handlers (either pre-defined or architecture
174 specific) are assigned to specific interrupts by the architecture either
321 which have no platform-specific IRQ handling quirks. If an architecture
385 The locking of chip registers is up to the architecture that defines the
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| /linux/arch/arm64/include/asm/ |
| H A D | kgdb.h | 45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
51 * RES0.". RES0 is heavily used in the ARM architecture documents as a
52 * way to leave space for future architecture changes. So to translate a
53 * little for people who don't spend their spare time reading ARM architecture
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