| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ |
| H A D | spec_operation.json | 12 "BriefDescription": "This event counts every architecturally executed instruction."
16 "BriefDescription": "This event counts every speculatively executed micro-operation."
20 … "BriefDescription": "This event counts architecturally executed load-exclusive instructions."
24 … "BriefDescription": "This event counts architecturally executed store-exclusive instructions."
28 …"BriefDescription": "This event counts architecturally executed memory-reading instructions, as de…
32 …"BriefDescription": "This event counts architecturally executed memory-writing instructions, as de…
36 …iption": "This event counts architecturally executed memory-reading instructions and memory-writin…
40 …"BriefDescription": "This event counts architecturally executed integer data-processing instructio…
44 …"BriefDescription": "This event counts architecturally executed Advanced SIMD data-processing inst…
48 …"BriefDescription": "This event counts architecturally executed floating-point data-processing ins…
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
[all …]
|
| /linux/arch/arm/include/asm/ |
| H A D | virt.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
|
| /linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
24 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
29 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
36 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
39 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
42 - index encodes the unique redistributor region index
43 - flags: reserved for future use, currently 0
44 - base field encodes bits [51:16] of the guest physical base address
[all …]
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,arch_timer_mmio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
[all …]
|
| /linux/arch/parisc/kernel/ |
| H A D | vmlinux.lds.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 107 …architecturally defined event. This event counts the number of retired branch instructions that we…
116 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
126 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
136 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
146 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
156 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
164 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
189 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
206 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
215 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
[all …]
|
| /linux/Documentation/arch/x86/ |
| H A D | entry_64.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to common_interrupt()
[all …]
|
| /linux/arch/x86/lib/ |
| H A D | retpoline.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <asm/asm-offsets.h>
10 #include <asm/nospec-branch.h>
64 #include <asm/GEN-for-each-reg.h>
71 #include <asm/GEN-for-each-reg.h>
94 #include <asm/GEN-for-each-reg.h>
101 #include <asm/GEN-for-each-reg.h>
120 #include <asm/GEN-for-each-reg.h>
127 #include <asm/GEN-for-each-reg.h>
152 .skip 32 - (__x86_indirect_its_thunk_\reg - 1b), 0xcc /* skip to the next upper half */
[all …]
|
| /linux/Documentation/trace/coresight/ |
| H A D | coresight-ect.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
[all …]
|
| H A D | coresight-etm4x-reference.rst | 11 ---------------------------
20 ----
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
86 ----
[all …]
|
| /linux/drivers/clocksource/ |
| H A D | arc_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
75 * defined in arch/arc/kernel/mcip.c in arc_read_gfrc()
110 pr_warn("Global-64-bit-Ctr clocksource not detected\n"); in arc_cs_setup_gfrc()
[all …]
|
| /linux/arch/arm/probes/ |
| H A D | decode.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* str_pc_offset is architecturally defined from ARMv7 onwards */
32 /* We need a run-time check to determine str_pc_offset */
41 long cpsr = regs->ARM_cpsr; in bx_write_pc()
49 regs->ARM_cpsr = cpsr; in bx_write_pc()
50 regs->ARM_pc = pcv; in bx_write_pc()
62 /* We need run-time testing to determine if load_write_pc() should interwork. */
73 regs->ARM_pc = pcv; in load_write_pc()
90 /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
101 regs->ARM_pc = pcv; in alu_write_pc()
[all …]
|
| /linux/tools/testing/selftests/kvm/x86/ |
| H A D | pmu_counters_test.c | 1 // SPDX-License-Identifier: GPL-2.0
58 * compiler often thinks the feature definitions aren't compile-time constants.
155 * bizarre with an architecturally valid, but unsupported, version.
162 * one "hit", assert that its count is non-zero. If an event isn't supported in guest_assert_event_count()
179 /* Relax precise count check due to VM-EXIT/VM-ENTRY overcount issue */ in guest_assert_event_count()
186 /* Relax precise count check due to VM-EXIT/VM-ENTR in guest_assert_event_count()
[all...] |
| /linux/arch/arm64/mm/ |
| H A D | fault.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
23 #include <linux/page-flags.h>
39 #include <asm/debug-monitors.h>
114 esr_to_fault_info(esr)->name); in mem_abort_decode()
124 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
126 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
140 mm = current->active_mm; in show_pte()
155 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", in show_pte()
210 * like __set_ptes(), the PTE is never changed from no-exec to exec here.
[all …]
|
| /linux/Documentation/arch/loongarch/ |
| H A D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
10 (PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
[all …]
|
| /linux/arch/arm64/kernel/ |
| H A D | fpsimd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
70 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
86 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware
99 * - the task gets scheduled in; if both the task's fpsimd_cpu field
100 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
104 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
110 * - the task executes an ordinary syscall; upon return to userland, the
114 * - the task executes a syscall which executes some NEON instructions; this is
116 * register contents to memory, clears the fpsimd_last_state per-cpu variable
119 * - the task gets preempted after kernel_neon_end() is called; as we have not
[all …]
|
| /linux/Documentation/arch/arm64/ |
| H A D | booting.rst | 13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
33 ---------------------------
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
96 - code0/code1 are responsible for branching to stext.
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | cache.json | 16 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
22 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
26 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
32 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
36 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
[all...] |
| /linux/arch/x86/kernel/cpu/ |
| H A D | amd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/platform_data/x86/amd-fch.h>
20 #include <asm/spec-ctrl.h>
23 #include <asm/pci-direct.h>
77 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
103 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ in init_amd_k5()
106 if (c->x86_model == 9 || c->x86_model == 10) { in init_amd_k5()
117 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); in init_amd_k6()
119 if (c->x86_model < 6) { in init_amd_k6()
120 /* Based on AMD doc 20734R - June 2000 */ in init_amd_k6()
[all …]
|
| /linux/drivers/perf/arm_cspmu/ |
| H A D | arm_cspmu.c | 1 // SPDX-License-Identifier: GPL-2.0
13 * - ARM CoreSight PMU architecture document number: ARM IHI 0091 A.a-00bet0.
14 * - APMT document number: ARM DEN0117.
19 * Copyright (c) 2022-2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
27 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRVNAME "arm-cs-arch-pmu"
54 (idx & (ARM_CSPMU_SET_CLR_COUNTER_NUM - 1))
60 * Maximum poll count for reading counter value using high-low-high sequence.
81 * With FEAT_CSPMU_EXT32, all of the MMIO registers are 32-bit except the
82 * counter registers, which are either 32-bit or 64-bit depending on the value
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | cache.json | 45 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
51 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
55 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
61 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
65 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | cache.json | 26 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
32 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
36 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
42 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
46 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
[all...] |
| /linux/drivers/nvdimm/ |
| H A D | region_devs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
15 #include "nd-core.h"
19 * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is
22 #include <linux/io-64-nonatomic-hi-lo.h>
32 nvdimm->num_flush, nvdimm->num_flush == 1 ? "" : "es"); in nvdimm_map_flush()
33 for (i = 0; i < (1 << ndrd->hints_shift); i++) { in nvdimm_map_flush()
34 struct resource *res = &nvdimm->flush_wpq[i]; in nvdimm_map_flush()
35 unsigned long pfn = PHYS_PFN(res->start); in nvdimm_map_flush()
40 struct resource *res_j = &nvdimm->flush_wpq[j]; in nvdimm_map_flush()
[all …]
|
| /linux/tools/testing/selftests/kvm/include/x86/ |
| H A D | processor.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <asm/msr-index.h>
43 #define X86_EFLAGS_FIXED BIT(1) /* Bit 1 - always on */
127 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
154 * Basic Leafs, a.k.a. Intel defined
205 * Extended Leafs, a.k.a. AMD defined
237 * KVM defined paravir
[all...] |