Home
last modified time | relevance | path

Searched +full:ar9132 +full:- +full:misc +full:- +full:intc (Results 1 – 3 of 3) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dqca,ar7100-misc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
10 - Alban Bedel <albeu@free.fr>
11 - Alexander Couzens <lynxis@fe80.eu>
14 The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary
20 - items:
21 - const: qca,ar9132-misc-intc
[all …]
H A Dqca,ath79-misc-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
23 interrupt-controller@18060010 {
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
[all …]
/freebsd/sys/contrib/device-tree/src/mips/qca/
H A Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
5 compatible = "qca,ar9132";
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
[all …]