Searched +full:ar9132 +full:- +full:ddr +full:- +full:controller (Results 1 – 5 of 5) sorted by relevance
/freebsd/sys/contrib/device-tree/src/mips/qca/ |
H A D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 5 compatible = "qca,ar9132"; 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
H A D | qca,ath79-ddr-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to 14 flush the FIFO between various devices and the DDR. This is mainly used by 15 the IRQ controller to flush the FIFO before running the interrupt handler of 21 - items: [all …]
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H A D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller 3 The DDR controller of the AR7xxx and AR9xxx families provides an interface 4 to flush the FIFO between various devices and the DDR. This is mainly used 5 by the IRQ controller to flush the FIFO before running the interrupt handler 10 - compatible: has to be "qca,<soc-type>-ddr-controller", 11 "qca,[ar7100|ar7240]-ddr-controller" as fallback. 12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as 13 fallback, otherwise "qca,ar7240-ddr-controller" should be used. 14 - reg: Base address and size of the controller's memory area 15 - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode [all …]
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
H A D | qca,ath79-cpu-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller 3 On most SoC the IRQ controller need to flush the DDR FIFO before running 5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. 9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc" 11 - interrupt-controller : Identifies the node as an interrupt controller 12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write 22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for 23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt 28 interrupt-controller { [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | qca,ath79-pll.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. 6 - compatible: has to be "qca,<soctype>-pll" and one of the following 8 - "qca,ar7100-pll" 9 - "qca,ar7240-pll" 10 - "qca,ar9130-pll" 11 - "qca,ar9330-pll" 12 - "qca,ar9340-pll" 13 - "qca,qca9550-pll" 14 - reg: Base address and size of the controllers memory area [all …]
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