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/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
38 TX, RX interrupt lines for each UART APDMA channel
43 description: Must contain one entry for the APDMA main clock
47 const: apdma
52 The first cell specifies the UART APDMA channel number
56 Number of virtual channels of the UART APDMA controller
61 description: Enable 33-bits UART APDMA support
89 apdma: dma-controller@11000400 {
118 clock-names = "apdma";
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi303 dmas = <&apdma 10
304 &apdma 11>;
383 apdma: dma-controller@11000400 { label
412 clock-names = "apdma";
432 dmas = <&apdma 0
433 &apdma 1>;
445 dmas = <&apdma 2
446 &apdma 3>;
458 dmas = <&apdma 4
459 &apdma 5>;
[all …]
H A Dmt8365.dtsi511 apdma: dma-controller@11000280 { label
527 clock-names = "apdma";
537 dmas = <&apdma 0>, <&apdma 1>;
548 dmas = <&apdma 2>, <&apdma 3>;
559 dmas = <&apdma 4>, <&apdma 5>;
/linux/drivers/dma/mediatek/
H A DMakefile2 obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
H A DKconfig30 tristate "MediaTek SoCs APDMA support for UART"
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-pericfg.c42 GATE_MTK(CLK_PERI_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
H A Dclk-mt8516.c550 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
H A Dclk-mt8167.c759 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),