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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
[all …]
H A Dintel,phy-keembay-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
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H A Dmediatek,smi-common.txt11 register which control the iommu port is at each larb's register base. But
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
20 "mediatek,mt2712-smi-common"
21 "mediatek,mt6779-smi-common"
22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 "mediatek,mt8167-smi-common"
24 "mediatek,mt8173-smi-common"
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the address space
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
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H A Dbrcm,kona-ccu.txt9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
20 Shall define the base and range of the address space
22 - #clock-cells
23 Shall have value <1>. The permitted clock-specifier values
25 - clock-output-names
32 compatible = "brcm,bcm11351-slave-ccu";
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/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
[all …]
H A Drockchip-pcie-ep.txt4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/freebsd/sys/contrib/device-tree/src/arc/
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dcv18xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
24 d-cache-block-size = <64>;
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dzx2967-thermal.txt4 - compatible: should be one of the following.
5 * zte,zx296718-thermal
6 - reg: physical base address of the controller and length of memory mapped
8 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "topcrm" for the topcrm clock.
10 "apb" for the apb clock.
11 - #thermal-sensor-cells: must be 0.
13 Please note: slope coefficient defined in thermal-zones section need to be
19 compatible = "zte,zx296718-thermal";
22 clock-names = "topcrm", "apb";
[all …]
H A Drockchip-thermal.txt4 - compatible : should be "rockchip,<name>-tsadc"
5 "rockchip,px30-tsadc": found on PX30 SoCs
6 "rockchip,rv1108-tsadc": found on RV1108 SoCs
7 "rockchip,rk3228-tsadc": found on RK3228 SoCs
8 "rockchip,rk3288-tsadc": found on RK3288 SoCs
9 "rockchip,rk3328-tsadc": found on RK3328 SoCs
10 "rockchip,rk3368-tsadc": found on RK3368 SoCs
11 "rockchip,rk3399-tsadc": found on RK3399 SoCs
12 - reg : physical base address of the controller and length of memory mapped
14 - interrupts : The interrupt number to the cpu. The interrupt specifier format
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_hdmi.txt1 Device-Tree bindings for drm hdmi driver
4 - compatible: value should be one among the following:
5 1) "samsung,exynos4210-hdmi"
6 2) "samsung,exynos4212-hdmi"
7 3) "samsung,exynos5420-hdmi"
8 4) "samsung,exynos5433-hdmi"
9 - reg: physical base address of the hdmi and length of memory mapped
11 - interrupts: interrupt number to the cpu.
12 - hpd-gpios: following information about the hotplug gpio pin.
16 - ddc: phandle to the hdmi ddc node
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
28 - description: Module Clock
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21 - enum:
22 - renesas,r9a07g043-csi2 # RZ/G2UL
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear300.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear300-pinmux";
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
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