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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
63 compatible = "andestech,cpu-intc",
71 compatible = "andestech,ax45mp", "riscv";
89 compatible = "andestech,cpu-intc",
97 compatible = "andestech,ax45mp", "riscv";
115 compatible = "andestech,cpu-intc",
131 compatible = "andestech,qilai-plmt", "andestech,plmt0";
140 compatible = "andestech,qilai-ax45mp-cache",
[all …]
H A Dqilai-voyager.dts10 compatible = "andestech,voyager", "andestech,qilai";
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dandestech,plicsw.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
19 - Ben Zong-You Xie <ben717@andestech.com>
25 - andestech,qilai-plicsw
26 - const: andestech,plicsw
48 compatible = "andestech,qilai-plicsw", "andestech,plicsw";
H A Driscv,cpu-intc.yaml41 - const: andestech,cpu-intc
/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml4 $id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
17 - Ben Zong-You Xie <ben717@andestech.com>
23 - andestech,qilai-plmt
24 - const: andestech,plmt0
47 compatible = "andestech,qilai-plmt", "andestech,plmt0";
/linux/Documentation/devicetree/bindings/riscv/
H A Dandes.yaml10 - Ben Zong-You Xie <ben717@andestech.com>
22 - andestech,voyager
23 - const: andestech,qilai
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
133 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
146 compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
/linux/Documentation/devicetree/bindings/net/
H A Dfaraday,ftmac.txt7 "andestech,atmac100"
/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml124 - andestech,uart16550
310 compatible = "andestech,uart16550", "ns16550a";
/linux/drivers/irqchip/
H A Dirq-riscv-intc.c239 if (of_device_is_compatible(node, "andestech,cpu-intc")) { in riscv_intc_init()
249 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
H A Dirq-sifive-plic.c433 { .compatible = "andestech,nceplic100",
/linux/drivers/cache/
H A Dax45mp_cache.c175 { .compatible = "andestech,ax45mp-cache" },
/linux/arch/riscv/kernel/
H A Dmodule-sections.c5 * Copyright (C) 2018 Andes Technology Corporation <zong@andestech.com>
/linux/
H A DMAINTAINERS22062 M: Ben Zong-You Xie <ben717@andestech.com>
22065 F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
22067 F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml