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Searched full:andestech (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/cache/
H A Dandestech,ax45mp-cache.yaml5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
8 title: Andestech AX45MP L2 Cache Controller
23 - andestech,ax45mp-cache
32 - andestech,qilai-ax45mp-cache
34 - const: andestech,ax45mp-cache
76 const: andestech,qilai-ax45mp-cache
90 compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
133 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
146 compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml57 - const: andestech,nceplic100
126 - andestech,nceplic100
H A Driscv,cpu-intc.yaml41 - const: andestech,cpu-intc
/linux/Documentation/devicetree/bindings/net/
H A Dfaraday,ftmac.txt7 "andestech,atmac100"
/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml80 - andestech,uart16550
269 compatible = "andestech,uart16550", "ns16550a";
/linux/drivers/irqchip/
H A Dirq-riscv-intc.c239 if (of_device_is_compatible(node, "andestech,cpu-intc")) { in riscv_intc_init()
249 IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
H A Dirq-sifive-plic.c429 { .compatible = "andestech,nceplic100",
/linux/drivers/cache/
H A Dax45mp_cache.c175 { .compatible = "andestech,ax45mp-cache" },
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml48 - andestech,ax45mp
H A Dextensions.yaml663 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
/linux/arch/riscv/kernel/
H A Dmodule-sections.c5 * Copyright (C) 2018 Andes Technology Corporation <zong@andestech.com>
/linux/Documentation/devicetree/bindings/
H A Dvendor-prefixes.yaml128 "^andestech,.*":