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Searched +full:am654 +full:- +full:mailbox (Results 1 – 7 of 7) sorted by relevance

/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,secure-proxy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nishanth Menon <nm@ti.com>
13 The Texas Instruments' secure proxy is a mailbox controller that has
16 called "threads" or "proxies" - each instance is unidirectional and is
22 pattern: "^mailbox@[0-9a-f]+$"
25 const: ti,am654-secure-proxy
27 "#mbox-cells":
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H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
35 lines can also be routed to different processor sub-systems on DRA7xx as they
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
40 - ti,am62-r5fss
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/linux/drivers/phy/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
58 the mailbox. The mailbox is present only in omap4 and the register to
/linux/drivers/mailbox/
H A Domap-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP mailbox driver
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
26 #include "mailbox.h"
97 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
103 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
106 /* Mailbox FIFO handle functions */
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
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H A Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/soc/ti/ti-msgmgr.h>
41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
53 * struct ti_msgmgr_desc - Description of message manager integration
92 * struct ti_queue_inst - Description of a queue instance
102 * @chan: Mailbox channel
122 * struct ti_msgmgr_inst - Description of a Message Manager Instance
132 * @mbox: Mailbox Controller
148 * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages
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