Searched +full:al5d +full:- +full:1 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | allegro.txt | 1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
18 - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
22 al5e: video-codec@a0009000 {
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| H A D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
23 - items:
24 - const: allegro,al5e-1.1
25 - const: allegro,al5e
26 - items:
27 - const: allegro,al5d-1.1
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