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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
32 0x1: half-word (16bit)
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/freebsd/sys/contrib/device-tree/Bindings/dma/stm32/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
32 0x1: half-word (16bit)
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Int…
40 … (0x1<<1) // This bit masks, when set, the Int…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
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/freebsd/sys/dev/msk/
H A Dif_msk.c17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
81 /*-
171 "SK-9Sxx Gigabit Ethernet" },
173 "SK-9Exx Gigabit Ethernet"},
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers()
227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers()
238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
242 extoff = -1; in ar9300_get_channel_centers()
245 centers->ctl_center = in ar9300_get_channel_centers()
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); in ar9300_get_channel_centers()
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