address\-translation (full) in projects: linux

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Searched +full:address +full:- +full:translation (Results 1 – 25 of 673) sorted by relevance

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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A D	mmu.json	3 "PublicDescription": "Duration of a translation table walk handled by the MMU", 6 "BriefDescription": "Duration of a translation table walk handled by the MMU" 9 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe… 12 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe… 15 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe… 18 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe… 21 "PublicDescription": "Duration of a translation table walk requested by the LSU", 24 "BriefDescription": "Duration of a translation table walk requested by the LSU" 27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side", 30 "BriefDescription": "Duration of a translation table walk requested by the instruction side" [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	virtual-memory.json	23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 41 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 50 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 59 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 84 …e number of page walks completed due to stores whose address translations missed in all Translatio… 93 …e number of page walks completed due to stores whose address translations missed in all Translatio… 102 …e number of page walks completed due to stores whose address translations missed in all Translatio… 111 …e number of page walks completed due to stores whose address translations missed in all Translatio… 120 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 41 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 50 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 59 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 84 …e number of page walks completed due to stores whose address translations missed in all Translatio… 93 …e number of page walks completed due to stores whose address translations missed in all Translatio… 102 …e number of page walks completed due to stores whose address translations missed in all Translatio… 111 …e number of page walks completed due to stores whose address translations missed in all Translatio… 120 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", [all …]
/linux/Documentation/admin-guide/RAS/
H A D	address-translation.rst	`1 .. SPDX-License-Identifier: GPL-2.0 3 Address translation 7 ------- 9 Zen-based AMD systems include a Data Fabric that manages the layout of 12 These devices may provide a "normalized", i.e. device physical, address 14 a system physical address for the kernel to action on the memory. 16 AMD Address Translation Library (CONFIG_AMD_ATL) provides translation for 19 Glossary of acronyms used in address translation for Zen-based systems 22 * COD = Cluster-on-Die`
/linux/Documentation/devicetree/bindings/bus/
H A D	socionext,uniphier-system-bus.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The UniPhier System Bus is an external bus that connects on-board devices to 11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and 15 controller registers provide the control for the translation from the offset 16 within each bank to the CPU-viewed address. The needed setup includes the 17 base address, the size of each bank. Optionally, some timing parameters can 21 - Masahiro Yamada <yamada.masahiro@socionext.com> [all …]
H A D	mvebu-mbus.txt	`6 - compatible: Should be set to one of the following: 7 marvell,armada370-mbus 8 marvell,armadaxp-mbus 9 marvell,armada375-mbus 10 marvell,armada380-mbus 11 marvell,kirkwood-mbus 12 marvell,dove-mbus 13 marvell,orion5x-88f5281-mbus 14 marvell,orion5x-88f5182-mbus 15 marvell,orion5x-88f5181-mbus [all …]`
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	virtual-memory.json	23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 41 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 66 …e number of page walks completed due to stores whose address translations missed in all Translatio… 75 …e number of page walks completed due to stores whose address translations missed in all Translatio… 84 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 109 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 118 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 127 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 136 …k start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walk…
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	virtual-memory.json	23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 41 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 66 …e number of page walks completed due to stores whose address translations missed in all Translatio… 75 …e number of page walks completed due to stores whose address translations missed in all Translatio… 84 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 109 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 118 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 127 …age walks completed due to instruction fetches whose address translations missed in all Translatio… 136 …k start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walk…
/linux/Documentation/devicetree/bindings/iommu/
H A D	iommu.txt	10 * Remap address space to allow devices to access physical memory ranges that 13 Example: 32-bit DMA to 64-bit physical addresses 15 * Implement scatter-gather at page level granularity so that the device does 20 address regions. 22 * Provide address space isolation between multiple contexts. 29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices 30 typically have a fixed association to the master device, whereas multiple- 34 "dma-ranges" property that describes how the physical address space of the 35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a 39 -------------------- [all …]
/linux/Documentation/scsi/
H A D	aha152x.rst	`1 .. SPDX-License-Identifier: GPL-2.0 5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x) 8 Copyright \|copy\| 1993-1999 Jürgen Fischer <fischer@norbit.de> 14 bottom-half handler complete()). 26 IOPORT base io address (0x340/0x140) 27 IRQ interrupt level (9-12; default 11) 28 SCSI_ID scsi id of controller (0-7; default 7) 33 EXT_TRANS: enable extended translation (0/1: default 0 [off]) 42 - DAUTOCONF 43 use configuration the controller reports (AHA-152x only) [all …]`
/linux/Documentation/virt/kvm/x86/
H A D	mmu.rst	`1 .. SPDX-License-Identifier: GPL-2.0 13 - correctness: 18 - security: 21 - performance: 23 - scaling: 25 - hardware: 27 - integration: 31 - dirty tracking: 33 and framebuffer-based displays 34 - footprint: [all …]`
/linux/drivers/acpi/acpica/
H A D	rsdumpinfo.c	1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 4 * Module Name: rsdumpinfo - Tables used to display resource descriptors. 59 "Start-Dependent-Functions", NULL}, 70 "End-Dependent-Functions", NULL} 75 {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(io.io_decode), "Address Decoding", 77 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.minimum), "Address Minimum", NULL}, 78 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.maximum), "Address Maximum", NULL}, 80 {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(io.address_length), "Address Length", 87 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_io.address), "Address", NULL}, 89 "Address Length", NULL} [all …]
H A D	rsaddr.c	`1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 4 * Module Name: rsaddr - Address resource descriptors (16/32/64) 17 * acpi_rs_convert_address16 - All WORD (16-bit) address resources 29 /* Resource Type, General Flags, and Type-Specific Flags / 35 Address Granularity 36 * Address Range Minimum 37 * Address Range Maximum 38 * Address Translation Offset 39 * Address Length 41 {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.address16.address.granularity), [all …]`
/linux/Documentation/driver-api/
H A D	ntb.rst	5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects 6 the separate memory systems of two or more computers to the same PCI-Express 8 registers and memory translation windows, as well as non common features like 9 scratchpad and message registers. Scratchpad registers are read-and-writable 11 exchange a small amount of information at a fixed address. Message registers can 36 ---------------------------------------- 42 inbound translation configured on the local ntb port and outbound translation 46 Inbound translation: 50 \| dma-mapped \|-ntb_mw_set_trans(addr) \| 52 \| (addr) \|<======\| MW xlat addr \|<====\| MW base addr \|<== memory-mapped IO [all …]
/linux/arch/arm64/kvm/
H A D	stacktrace.c	`1 /* SPDX-License-Identifier: GPL-2.0-only / 7 1) Non-protected nVHE mode - the host can directly access the 12 * 2) pKVM (protected nVHE) mode - the host cannot directly access 29 unsigned long low = (unsigned long)stacktrace_info->overflow_stack_base; in stackinfo_get_overflow() 53 unsigned long low = (unsigned long)stacktrace_info->stack_base; in stackinfo_get_hyp() 74 * kvm_nvhe_stack_kern_va - Conver [all...]`
/linux/drivers/dma/fsl-dpaa2-qdma/
H A D	dpaa2-qdma.h	1 /* SPDX-License-Identifier: GPL-2.0 / 25 u32 rbpcmd; / Route-by-port command / 38 #define QMAN_FD_BMT_ENABLE BIT(15) / bypass memory translation / 39 #define QMAN_FD_BMT_DISABLE (0) / bypass memory translation / 54 #define QMAN_FD_VA_ENABLE BIT(14) / Address used is virtual address / 55 #define QMAN_FD_VA_DISABLE (0)/ Address used is a real address / 56 / Flow Context: 49bit physical address / 58 #define QMAN_FD_CBMT_DISABLE (0) / Flow Context: 64bit virtual address / 63 #define QDMA_FL_BMT_ENABLE BIT(15) / enable bypass memory translation / 64 #define QDMA_FL_BMT_DISABLE (0x0) / enable bypass memory translation */ [all …]
/linux/Documentation/arch/arm64/
H A D	tagged-pointers.rst	10 addresses in the AArch64 translation system and their potential uses 13 The kernel configures the translation tables so that translations made 15 the virtual address ignored by the translation hardware. This frees up 20 -------------------------------------- 23 an address tag of 0x00, unless the application enables the AArch64 24 Tagged Address ABI explicitly 25 (Documentation/arch/arm64/tagged-address-abi.rst). 29 - pointer arguments to system calls, including pointers in structures 32 - the stack pointer (sp), e.g. when interpreting it to deliver a 35 - the frame pointer (x29) and frame records, e.g. when interpreting [all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A D	raideng.txt	3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID 11 - compatible: Should contain "fsl,raideng-v1.0" as the value 15 - reg: offset and length of the register set for the device 16 - ranges: standard ranges property specifying the translation 17 between child address space and parent address space 22 compatible = "fsl,raideng-v1.0"; 23 #address-cells = <1>; 24 #size-cells = <1>; 30 There must be a sub-node for each job queue present in RAID Engine 31 This node must be a sub-node of the main RAID Engine node [all …]
/linux/Documentation/admin-guide/mm/
H A D	concepts.rst	7 systems from MMU-less microcontrollers to supercomputers. The memory 12 address to a physical address. 23 address ranges. Besides, different CPU architectures, and even 25 of how these address ranges are defined. 36 address. When the CPU decodes an instruction that reads (or 38 address encoded in that instruction to a `physical` address that the 49 translation from a virtual address used by programs to the physical 50 memory address. The page tables are organized hierarchically. 56 register. When the CPU performs the address translation, it uses this 58 virtual address are used to index an entry in the top level page [all …]
/linux/drivers/ras/amd/atl/
H A D	core.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * AMD Address Translation Library 5 * core.c : Module init and base translation functions 25 dram_limit_addr = FIELD_GET(DF4_DRAM_LIMIT_ADDR, ctx->map.limit); in addr_over_limit() 27 dram_limit_addr = FIELD_GET(DF2_DRAM_LIMIT_ADDR, ctx->map.limit); in addr_over_limit() 30 dram_limit_addr \|= GENMASK(DF_DRAM_BASE_LIMIT_LSB - 1, 0); in addr_over_limit() 32 /* Is calculated system address above DRAM limit address? */ in addr_over_limit() 33 if (ctx->ret_addr > dram_limit_addr) { in addr_over_limit() 34 atl_debug(ctx, "Calculated address (0x%016llx) > DRAM limit (0x%016llx)", in addr_over_limit() 35 ctx->ret_addr, dram_limit_addr); in addr_over_limit() [all …]
/linux/Documentation/arch/x86/
H A D	sva.rst	1 .. SPDX-License-Identifier: GPL-2.0 17 PCIe Address Translation Services (ATS) along with Page Request Interface 19 application page-faults. For more information please refer to the PCIe 26 sync. When an ATS lookup fails for a virtual address, the device should 27 use the PRI in order to request the virtual address to be paged into the 29 translation before use. 34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits 39 executed in the hardware by SWQ interface, SIOV uses Process Address Space 40 ID (PASID), which is a 20-bit number defined by the PCIe SIG. 43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe [all …]
/linux/Documentation/devicetree/bindings/arm/
H A D	arm,coresight-catu.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm Coresight Address Translation Unit (CATU) 10 - Mathieu Poirier <mathieu.poirier@linaro.org> 11 - Mike Leach <mike.leach@linaro.org> 12 - Leo Yan <leo.yan@linaro.org> 13 - Suzuki K Poulose <suzuki.poulose@arm.com> 23 The CoreSight Address Translation Unit (CATU) translates addresses between an [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due… 8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due… 12 …"PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includ… 20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due… 24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due… 28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due… 32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due… 40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.… 44 … level 2 cache by cache maintenance operations that operate by a virtual address, or by external c…
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	virtual-memory.json	56 …mpleted page walks (1G sizes) caused by demand data loads. This implies address translations miss… 66 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 76 …eted page walks (2M/4M sizes) caused by demand data loads. This implies address translations miss… 86 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio… 96 …mpleted page walks (4K sizes) caused by demand data loads. This implies address translations miss… 106 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 175 …pleted page walks (1G sizes) caused by demand data stores. This implies address translations miss… 185 …e number of page walks completed due to stores whose address translations missed in all Translatio… 195 …ted page walks (2M/4M sizes) caused by demand data stores. This implies address translations miss… 205 …e number of page walks completed due to stores whose address translations missed in all Translatio… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	virtual-memory.json	7 …walks completed due to demand data loads (including SW prefetches) whose address translations miss… 16 …walks completed due to demand data loads (including SW prefetches) whose address translations miss… 25 …walks completed due to demand data loads (including SW prefetches) whose address translations miss… 43 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 52 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 61 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… 79 … (EPT), and does not count during the rest of the translation. The EPT is used for translating Gu… 88 …d a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an … 97 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla… 106 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla… [all …]

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