1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,rk3576"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 serial5 = &uart5; 39 serial6 = &uart6; 40 serial7 = &uart7; 41 serial8 = &uart8; 42 serial9 = &uart9; 43 serial10 = &uart10; 44 serial11 = &uart11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi2 = &spi2; 48 spi3 = &spi3; 49 spi4 = &spi4; 50 }; 51 52 xin32k: clock-xin32k { 53 compatible = "fixed-clock"; 54 clock-frequency = <32768>; 55 clock-output-names = "xin32k"; 56 #clock-cells = <0>; 57 }; 58 59 xin24m: clock-xin24m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <24000000>; 63 clock-output-names = "xin24m"; 64 }; 65 66 spll: clock-spll { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <702000000>; 70 clock-output-names = "spll"; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu-map { 78 cluster0 { 79 core0 { 80 cpu = <&cpu_l0>; 81 }; 82 core1 { 83 cpu = <&cpu_l1>; 84 }; 85 core2 { 86 cpu = <&cpu_l2>; 87 }; 88 core3 { 89 cpu = <&cpu_l3>; 90 }; 91 }; 92 cluster1 { 93 core0 { 94 cpu = <&cpu_b0>; 95 }; 96 core1 { 97 cpu = <&cpu_b1>; 98 }; 99 core2 { 100 cpu = <&cpu_b2>; 101 }; 102 core3 { 103 cpu = <&cpu_b3>; 104 }; 105 }; 106 }; 107 108 cpu_l0: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&scmi_clk SCMI_ARMCLK_L>; 115 operating-points-v2 = <&cluster0_opp_table>; 116 #cooling-cells = <2>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 }; 120 121 cpu_l1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x1>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <485>; 127 clocks = <&scmi_clk SCMI_ARMCLK_L>; 128 operating-points-v2 = <&cluster0_opp_table>; 129 cpu-idle-states = <&CPU_SLEEP>; 130 }; 131 132 cpu_l2: cpu@2 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x2>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <485>; 138 clocks = <&scmi_clk SCMI_ARMCLK_L>; 139 operating-points-v2 = <&cluster0_opp_table>; 140 cpu-idle-states = <&CPU_SLEEP>; 141 }; 142 143 cpu_l3: cpu@3 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x3>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <485>; 149 clocks = <&scmi_clk SCMI_ARMCLK_L>; 150 operating-points-v2 = <&cluster0_opp_table>; 151 cpu-idle-states = <&CPU_SLEEP>; 152 }; 153 154 cpu_b0: cpu@100 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a72"; 157 reg = <0x100>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 clocks = <&scmi_clk SCMI_ARMCLK_B>; 161 operating-points-v2 = <&cluster1_opp_table>; 162 #cooling-cells = <2>; 163 dynamic-power-coefficient = <320>; 164 cpu-idle-states = <&CPU_SLEEP>; 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a72"; 170 reg = <0x101>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 clocks = <&scmi_clk SCMI_ARMCLK_B>; 174 operating-points-v2 = <&cluster1_opp_table>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 }; 177 178 cpu_b2: cpu@102 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a72"; 181 reg = <0x102>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 clocks = <&scmi_clk SCMI_ARMCLK_B>; 185 operating-points-v2 = <&cluster1_opp_table>; 186 cpu-idle-states = <&CPU_SLEEP>; 187 }; 188 189 cpu_b3: cpu@103 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a72"; 192 reg = <0x103>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk SCMI_ARMCLK_B>; 196 operating-points-v2 = <&cluster1_opp_table>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 CPU_SLEEP: cpu-sleep { 204 compatible = "arm,idle-state"; 205 arm,psci-suspend-param = <0x0010000>; 206 entry-latency-us = <120>; 207 exit-latency-us = <250>; 208 min-residency-us = <900>; 209 local-timer-stop; 210 }; 211 }; 212 }; 213 214 cluster0_opp_table: opp-table-cluster0 { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-408000000 { 219 opp-hz = /bits/ 64 <408000000>; 220 opp-microvolt = <700000 700000 950000>; 221 clock-latency-ns = <40000>; 222 }; 223 224 opp-600000000 { 225 opp-hz = /bits/ 64 <600000000>; 226 opp-microvolt = <700000 700000 950000>; 227 clock-latency-ns = <40000>; 228 }; 229 230 opp-816000000 { 231 opp-hz = /bits/ 64 <816000000>; 232 opp-microvolt = <700000 700000 950000>; 233 clock-latency-ns = <40000>; 234 }; 235 236 opp-1008000000 { 237 opp-hz = /bits/ 64 <1008000000>; 238 opp-microvolt = <700000 700000 950000>; 239 clock-latency-ns = <40000>; 240 }; 241 242 opp-1200000000 { 243 opp-hz = /bits/ 64 <1200000000>; 244 opp-microvolt = <700000 700000 950000>; 245 clock-latency-ns = <40000>; 246 }; 247 248 opp-1416000000 { 249 opp-hz = /bits/ 64 <1416000000>; 250 opp-microvolt = <725000 725000 950000>; 251 clock-latency-ns = <40000>; 252 }; 253 254 opp-1608000000 { 255 opp-hz = /bits/ 64 <1608000000>; 256 opp-microvolt = <750000 750000 950000>; 257 clock-latency-ns = <40000>; 258 }; 259 260 opp-1800000000 { 261 opp-hz = /bits/ 64 <1800000000>; 262 opp-microvolt = <825000 825000 950000>; 263 clock-latency-ns = <40000>; 264 opp-suspend; 265 }; 266 267 opp-2016000000 { 268 opp-hz = /bits/ 64 <2016000000>; 269 opp-microvolt = <900000 900000 950000>; 270 clock-latency-ns = <40000>; 271 }; 272 273 opp-2208000000 { 274 opp-hz = /bits/ 64 <2208000000>; 275 opp-microvolt = <950000 950000 950000>; 276 clock-latency-ns = <40000>; 277 }; 278 }; 279 280 cluster1_opp_table: opp-table-cluster1 { 281 compatible = "operating-points-v2"; 282 opp-shared; 283 284 opp-408000000 { 285 opp-hz = /bits/ 64 <408000000>; 286 opp-microvolt = <700000 700000 950000>; 287 clock-latency-ns = <40000>; 288 opp-suspend; 289 }; 290 291 opp-600000000 { 292 opp-hz = /bits/ 64 <600000000>; 293 opp-microvolt = <700000 700000 950000>; 294 clock-latency-ns = <40000>; 295 }; 296 297 opp-816000000 { 298 opp-hz = /bits/ 64 <816000000>; 299 opp-microvolt = <700000 700000 950000>; 300 clock-latency-ns = <40000>; 301 }; 302 303 opp-1008000000 { 304 opp-hz = /bits/ 64 <1008000000>; 305 opp-microvolt = <700000 700000 950000>; 306 clock-latency-ns = <40000>; 307 }; 308 309 opp-1200000000 { 310 opp-hz = /bits/ 64 <1200000000>; 311 opp-microvolt = <700000 700000 950000>; 312 clock-latency-ns = <40000>; 313 }; 314 315 opp-1416000000 { 316 opp-hz = /bits/ 64 <1416000000>; 317 opp-microvolt = <712500 712500 950000>; 318 clock-latency-ns = <40000>; 319 }; 320 321 opp-1608000000 { 322 opp-hz = /bits/ 64 <1608000000>; 323 opp-microvolt = <737500 737500 950000>; 324 clock-latency-ns = <40000>; 325 }; 326 327 opp-1800000000 { 328 opp-hz = /bits/ 64 <1800000000>; 329 opp-microvolt = <800000 800000 950000>; 330 clock-latency-ns = <40000>; 331 }; 332 333 opp-2016000000 { 334 opp-hz = /bits/ 64 <2016000000>; 335 opp-microvolt = <862500 862500 950000>; 336 clock-latency-ns = <40000>; 337 }; 338 339 opp-2208000000 { 340 opp-hz = /bits/ 64 <2208000000>; 341 opp-microvolt = <925000 925000 950000>; 342 clock-latency-ns = <40000>; 343 }; 344 345 opp-2304000000 { 346 opp-hz = /bits/ 64 <2304000000>; 347 opp-microvolt = <950000 950000 950000>; 348 clock-latency-ns = <40000>; 349 }; 350 }; 351 352 gpu_opp_table: opp-table-gpu { 353 compatible = "operating-points-v2"; 354 355 opp-300000000 { 356 opp-hz = /bits/ 64 <300000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-400000000 { 361 opp-hz = /bits/ 64 <400000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-500000000 { 366 opp-hz = /bits/ 64 <500000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-600000000 { 371 opp-hz = /bits/ 64 <600000000>; 372 opp-microvolt = <700000 700000 850000>; 373 }; 374 375 opp-700000000 { 376 opp-hz = /bits/ 64 <700000000>; 377 opp-microvolt = <725000 725000 850000>; 378 }; 379 380 opp-800000000 { 381 opp-hz = /bits/ 64 <800000000>; 382 opp-microvolt = <775000 775000 850000>; 383 }; 384 385 opp-900000000 { 386 opp-hz = /bits/ 64 <900000000>; 387 opp-microvolt = <825000 825000 850000>; 388 }; 389 390 opp-950000000 { 391 opp-hz = /bits/ 64 <950000000>; 392 opp-microvolt = <850000 850000 850000>; 393 }; 394 }; 395 396 display_subsystem: display-subsystem { 397 compatible = "rockchip,display-subsystem"; 398 ports = <&vop_out>; 399 }; 400 401 firmware { 402 scmi: scmi { 403 compatible = "arm,scmi-smc"; 404 arm,smc-id = <0x82000010>; 405 shmem = <&scmi_shmem>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 409 scmi_clk: protocol@14 { 410 reg = <0x14>; 411 #clock-cells = <1>; 412 }; 413 }; 414 }; 415 416 hdmi_sound: hdmi-sound { 417 compatible = "simple-audio-card"; 418 simple-audio-card,name = "HDMI"; 419 simple-audio-card,format = "i2s"; 420 simple-audio-card,mclk-fs = <256>; 421 status = "disabled"; 422 423 simple-audio-card,codec { 424 sound-dai = <&hdmi>; 425 }; 426 427 simple-audio-card,cpu { 428 sound-dai = <&sai6>; 429 }; 430 }; 431 432 pinctrl: pinctrl { 433 compatible = "rockchip,rk3576-pinctrl"; 434 rockchip,grf = <&ioc_grf>; 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 439 gpio0: gpio@27320000 { 440 compatible = "rockchip,gpio-bank"; 441 reg = <0x0 0x27320000 0x0 0x200>; 442 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 443 gpio-controller; 444 gpio-ranges = <&pinctrl 0 0 32>; 445 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-controller; 447 #gpio-cells = <2>; 448 #interrupt-cells = <2>; 449 }; 450 451 gpio1: gpio@2ae10000 { 452 compatible = "rockchip,gpio-bank"; 453 reg = <0x0 0x2ae10000 0x0 0x200>; 454 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 455 gpio-controller; 456 gpio-ranges = <&pinctrl 0 32 32>; 457 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-controller; 459 #gpio-cells = <2>; 460 #interrupt-cells = <2>; 461 }; 462 463 gpio2: gpio@2ae20000 { 464 compatible = "rockchip,gpio-bank"; 465 reg = <0x0 0x2ae20000 0x0 0x200>; 466 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 467 gpio-controller; 468 gpio-ranges = <&pinctrl 0 64 32>; 469 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-controller; 471 #gpio-cells = <2>; 472 #interrupt-cells = <2>; 473 }; 474 475 gpio3: gpio@2ae30000 { 476 compatible = "rockchip,gpio-bank"; 477 reg = <0x0 0x2ae30000 0x0 0x200>; 478 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 479 gpio-controller; 480 gpio-ranges = <&pinctrl 0 96 32>; 481 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-controller; 483 #gpio-cells = <2>; 484 #interrupt-cells = <2>; 485 }; 486 487 gpio4: gpio@2ae40000 { 488 compatible = "rockchip,gpio-bank"; 489 reg = <0x0 0x2ae40000 0x0 0x200>; 490 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 491 gpio-controller; 492 gpio-ranges = <&pinctrl 0 128 32>; 493 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-controller; 495 #gpio-cells = <2>; 496 #interrupt-cells = <2>; 497 }; 498 }; 499 500 pmu_a53: pmu-a53 { 501 compatible = "arm,cortex-a53-pmu"; 502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 507 }; 508 509 pmu_a72: pmu-a72 { 510 compatible = "arm,cortex-a72-pmu"; 511 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 515 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 516 }; 517 518 psci { 519 compatible = "arm,psci-1.0"; 520 method = "smc"; 521 }; 522 523 timer { 524 compatible = "arm,armv8-timer"; 525 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 526 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 527 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 528 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 529 }; 530 531 soc { 532 compatible = "simple-bus"; 533 #address-cells = <2>; 534 #size-cells = <2>; 535 ranges; 536 537 pcie0: pcie@22000000 { 538 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 539 reg = <0x0 0x22000000 0x0 0x00400000>, 540 <0x0 0x2a200000 0x0 0x00010000>, 541 <0x0 0x20000000 0x0 0x00100000>; 542 reg-names = "dbi", "apb", "config"; 543 bus-range = <0x0 0xf>; 544 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 545 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 546 <&cru CLK_PCIE0_AUX>; 547 clock-names = "aclk_mst", "aclk_slv", 548 "aclk_dbi", "pclk", 549 "aux"; 550 device_type = "pci"; 551 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 558 #interrupt-cells = <1>; 559 interrupt-map-mask = <0 0 0 7>; 560 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 561 <0 0 0 2 &pcie0_intc 1>, 562 <0 0 0 3 &pcie0_intc 2>, 563 <0 0 0 4 &pcie0_intc 3>; 564 linux,pci-domain = <0>; 565 max-link-speed = <2>; 566 num-ib-windows = <8>; 567 num-viewport = <8>; 568 num-ob-windows = <2>; 569 num-lanes = <1>; 570 phys = <&combphy0_ps PHY_TYPE_PCIE>; 571 phy-names = "pcie-phy"; 572 power-domains = <&power RK3576_PD_PHP>; 573 ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 574 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 575 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 576 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 577 reset-names = "pwr", "pipe"; 578 #address-cells = <3>; 579 #size-cells = <2>; 580 status = "disabled"; 581 582 pcie0_intc: legacy-interrupt-controller { 583 interrupt-controller; 584 #address-cells = <0>; 585 #interrupt-cells = <1>; 586 interrupt-parent = <&gic>; 587 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 588 }; 589 }; 590 591 pcie1: pcie@22400000 { 592 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 593 reg = <0x0 0x22400000 0x0 0x00400000>, 594 <0x0 0x2a210000 0x0 0x00010000>, 595 <0x0 0x21000000 0x0 0x00100000>; 596 reg-names = "dbi", "apb", "config"; 597 bus-range = <0x20 0x2f>; 598 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 599 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 600 <&cru CLK_PCIE1_AUX>; 601 clock-names = "aclk_mst", "aclk_slv", 602 "aclk_dbi", "pclk", 603 "aux"; 604 device_type = "pci"; 605 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 611 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 612 #interrupt-cells = <1>; 613 interrupt-map-mask = <0 0 0 7>; 614 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 615 <0 0 0 2 &pcie1_intc 1>, 616 <0 0 0 3 &pcie1_intc 2>, 617 <0 0 0 4 &pcie1_intc 3>; 618 linux,pci-domain = <1>; 619 max-link-speed = <2>; 620 num-ib-windows = <8>; 621 num-viewport = <8>; 622 num-ob-windows = <2>; 623 num-lanes = <1>; 624 phys = <&combphy1_psu PHY_TYPE_PCIE>; 625 phy-names = "pcie-phy"; 626 power-domains = <&power RK3576_PD_SUBPHP>; 627 ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 628 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 629 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 630 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 631 reset-names = "pwr", "pipe"; 632 #address-cells = <3>; 633 #size-cells = <2>; 634 status = "disabled"; 635 636 pcie1_intc: legacy-interrupt-controller { 637 interrupt-controller; 638 #address-cells = <0>; 639 #interrupt-cells = <1>; 640 interrupt-parent = <&gic>; 641 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 642 }; 643 }; 644 645 usb_drd0_dwc3: usb@23000000 { 646 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 647 reg = <0x0 0x23000000 0x0 0x400000>; 648 clocks = <&cru CLK_REF_USB3OTG0>, 649 <&cru CLK_SUSPEND_USB3OTG0>, 650 <&cru ACLK_USB3OTG0>; 651 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 652 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 653 power-domains = <&power RK3576_PD_USB>; 654 resets = <&cru SRST_A_USB3OTG0>; 655 dr_mode = "otg"; 656 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 657 phy-names = "usb2-phy", "usb3-phy"; 658 phy_type = "utmi_wide"; 659 snps,dis_enblslpm_quirk; 660 snps,dis-u1-entry-quirk; 661 snps,dis-u2-entry-quirk; 662 snps,dis-u2-freeclk-exists-quirk; 663 snps,dis-del-phy-power-chg-quirk; 664 snps,dis-tx-ipgap-linecheck-quirk; 665 snps,parkmode-disable-hs-quirk; 666 snps,parkmode-disable-ss-quirk; 667 status = "disabled"; 668 }; 669 670 usb_drd1_dwc3: usb@23400000 { 671 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 672 reg = <0x0 0x23400000 0x0 0x400000>; 673 clocks = <&cru CLK_REF_USB3OTG1>, 674 <&cru CLK_SUSPEND_USB3OTG1>, 675 <&cru ACLK_USB3OTG1>; 676 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 677 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 678 power-domains = <&power RK3576_PD_PHP>; 679 resets = <&cru SRST_A_USB3OTG1>; 680 dr_mode = "otg"; 681 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 682 phy-names = "usb2-phy", "usb3-phy"; 683 phy_type = "utmi_wide"; 684 snps,dis_enblslpm_quirk; 685 snps,dis-u1-entry-quirk; 686 snps,dis-u2-entry-quirk; 687 snps,dis-u2-freeclk-exists-quirk; 688 snps,dis-del-phy-power-chg-quirk; 689 snps,dis-tx-ipgap-linecheck-quirk; 690 snps,dis_rxdet_inp3_quirk; 691 snps,parkmode-disable-hs-quirk; 692 snps,parkmode-disable-ss-quirk; 693 dma-coherent; 694 status = "disabled"; 695 }; 696 697 sys_grf: syscon@2600a000 { 698 compatible = "rockchip,rk3576-sys-grf", "syscon"; 699 reg = <0x0 0x2600a000 0x0 0x2000>; 700 }; 701 702 bigcore_grf: syscon@2600c000 { 703 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 704 reg = <0x0 0x2600c000 0x0 0x2000>; 705 }; 706 707 litcore_grf: syscon@2600e000 { 708 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 709 reg = <0x0 0x2600e000 0x0 0x2000>; 710 }; 711 712 cci_grf: syscon@26010000 { 713 compatible = "rockchip,rk3576-cci-grf", "syscon"; 714 reg = <0x0 0x26010000 0x0 0x2000>; 715 }; 716 717 gpu_grf: syscon@26016000 { 718 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 719 reg = <0x0 0x26016000 0x0 0x2000>; 720 }; 721 722 npu_grf: syscon@26018000 { 723 compatible = "rockchip,rk3576-npu-grf", "syscon"; 724 reg = <0x0 0x26018000 0x0 0x2000>; 725 }; 726 727 vo0_grf: syscon@2601a000 { 728 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 729 reg = <0x0 0x2601a000 0x0 0x2000>; 730 }; 731 732 usb_grf: syscon@2601e000 { 733 compatible = "rockchip,rk3576-usb-grf", "syscon"; 734 reg = <0x0 0x2601e000 0x0 0x1000>; 735 }; 736 737 php_grf: syscon@26020000 { 738 compatible = "rockchip,rk3576-php-grf", "syscon"; 739 reg = <0x0 0x26020000 0x0 0x2000>; 740 }; 741 742 pmu0_grf: syscon@26024000 { 743 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 744 reg = <0x0 0x26024000 0x0 0x1000>; 745 }; 746 747 pmu1_grf: syscon@26026000 { 748 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 749 reg = <0x0 0x26026000 0x0 0x1000>; 750 }; 751 752 pipe_phy0_grf: syscon@26028000 { 753 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 754 reg = <0x0 0x26028000 0x0 0x2000>; 755 }; 756 757 pipe_phy1_grf: syscon@2602a000 { 758 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 759 reg = <0x0 0x2602a000 0x0 0x2000>; 760 }; 761 762 usbdpphy_grf: syscon@2602c000 { 763 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 764 reg = <0x0 0x2602c000 0x0 0x2000>; 765 }; 766 767 usb2phy_grf: syscon@2602e000 { 768 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 769 reg = <0x0 0x2602e000 0x0 0x4000>; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 773 u2phy0: usb2-phy@0 { 774 compatible = "rockchip,rk3576-usb2phy"; 775 reg = <0x0 0x10>; 776 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 777 reset-names = "phy", "apb"; 778 clocks = <&cru CLK_PHY_REF_SRC>, 779 <&cru ACLK_MMU2>, 780 <&cru ACLK_SLV_MMU2>; 781 clock-names = "phyclk", "aclk", "aclk_slv"; 782 clock-output-names = "usb480m_phy0"; 783 #clock-cells = <0>; 784 status = "disabled"; 785 786 u2phy0_otg: otg-port { 787 #phy-cells = <0>; 788 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 792 status = "disabled"; 793 }; 794 }; 795 796 u2phy1: usb2-phy@2000 { 797 compatible = "rockchip,rk3576-usb2phy"; 798 reg = <0x2000 0x10>; 799 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 800 reset-names = "phy", "apb"; 801 clocks = <&cru CLK_PHY_REF_SRC>, 802 <&cru ACLK_MMU1>, 803 <&cru ACLK_SLV_MMU1>; 804 clock-names = "phyclk", "aclk", "aclk_slv"; 805 clock-output-names = "usb480m_phy1"; 806 #clock-cells = <0>; 807 status = "disabled"; 808 809 u2phy1_otg: otg-port { 810 #phy-cells = <0>; 811 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 815 status = "disabled"; 816 }; 817 }; 818 }; 819 820 hdptxphy_grf: syscon@26032000 { 821 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 822 reg = <0x0 0x26032000 0x0 0x100>; 823 }; 824 825 vo1_grf: syscon@26036000 { 826 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 827 reg = <0x0 0x26036000 0x0 0x100>; 828 clocks = <&cru PCLK_VO1_ROOT>; 829 }; 830 831 sdgmac_grf: syscon@26038000 { 832 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 833 reg = <0x0 0x26038000 0x0 0x1000>; 834 }; 835 836 ioc_grf: syscon@26040000 { 837 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 838 reg = <0x0 0x26040000 0x0 0xc000>; 839 }; 840 841 cru: clock-controller@27200000 { 842 compatible = "rockchip,rk3576-cru"; 843 reg = <0x0 0x27200000 0x0 0x50000>; 844 #clock-cells = <1>; 845 #reset-cells = <1>; 846 847 assigned-clocks = 848 <&cru CLK_AUDIO_FRAC_1_SRC>, 849 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 850 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 851 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 852 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 853 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 854 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 855 <&cru ACLK_PHP_ROOT>; 856 assigned-clock-parents = <&cru PLL_AUPLL>; 857 assigned-clock-rates = 858 <0>, 859 <1188000000>, <1000000000>, 860 <786432000>, <18432000>, 861 <96000000>, <128000000>, 862 <45158400>, <49152000>, 863 <500000000>, <250000000>, 864 <100000000>, <500000000>, 865 <250000000>; 866 }; 867 868 i2c0: i2c@27300000 { 869 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 870 reg = <0x0 0x27300000 0x0 0x1000>; 871 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 872 clock-names = "i2c", "pclk"; 873 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&i2c0m0_xfer>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 uart1: serial@27310000 { 882 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 883 reg = <0x0 0x27310000 0x0 0x100>; 884 reg-shift = <2>; 885 reg-io-width = <4>; 886 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 887 clock-names = "baudclk", "apb_pclk"; 888 dmas = <&dmac0 8>, <&dmac0 9>; 889 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&uart1m0_xfer>; 892 status = "disabled"; 893 }; 894 895 pmu: power-management@27380000 { 896 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 897 reg = <0x0 0x27380000 0x0 0x800>; 898 899 power: power-controller { 900 compatible = "rockchip,rk3576-power-controller"; 901 #power-domain-cells = <1>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 power-domain@RK3576_PD_NPU { 906 reg = <RK3576_PD_NPU>; 907 #power-domain-cells = <1>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 power-domain@RK3576_PD_NPUTOP { 912 reg = <RK3576_PD_NPUTOP>; 913 clocks = <&cru ACLK_RKNN0>, 914 <&cru ACLK_RKNN1>, 915 <&cru ACLK_RKNN_CBUF>, 916 <&cru CLK_RKNN_DSU0>, 917 <&cru HCLK_RKNN_CBUF>, 918 <&cru HCLK_RKNN_ROOT>, 919 <&cru HCLK_NPU_CM0_ROOT>, 920 <&cru PCLK_NPUTOP_ROOT>; 921 pm_qos = <&qos_npu_mcu>, 922 <&qos_npu_nsp0>, 923 <&qos_npu_nsp1>, 924 <&qos_npu_m0ro>, 925 <&qos_npu_m1ro>; 926 #power-domain-cells = <1>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 930 power-domain@RK3576_PD_NPU0 { 931 reg = <RK3576_PD_NPU0>; 932 clocks = <&cru HCLK_RKNN_ROOT>, 933 <&cru ACLK_RKNN0>; 934 pm_qos = <&qos_npu_m0>; 935 #power-domain-cells = <0>; 936 }; 937 power-domain@RK3576_PD_NPU1 { 938 reg = <RK3576_PD_NPU1>; 939 clocks = <&cru HCLK_RKNN_ROOT>, 940 <&cru ACLK_RKNN1>; 941 pm_qos = <&qos_npu_m1>; 942 #power-domain-cells = <0>; 943 }; 944 }; 945 }; 946 947 power-domain@RK3576_PD_GPU { 948 reg = <RK3576_PD_GPU>; 949 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 950 pm_qos = <&qos_gpu>; 951 #power-domain-cells = <0>; 952 }; 953 954 power-domain@RK3576_PD_NVM { 955 reg = <RK3576_PD_NVM>; 956 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 957 pm_qos = <&qos_emmc>, 958 <&qos_fspi0>; 959 #power-domain-cells = <1>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 963 power-domain@RK3576_PD_SDGMAC { 964 reg = <RK3576_PD_SDGMAC>; 965 clocks = <&cru ACLK_HSGPIO>, 966 <&cru ACLK_GMAC0>, 967 <&cru ACLK_GMAC1>, 968 <&cru CCLK_SRC_SDIO>, 969 <&cru CCLK_SRC_SDMMC0>, 970 <&cru HCLK_HSGPIO>, 971 <&cru HCLK_SDIO>, 972 <&cru HCLK_SDMMC0>, 973 <&cru PCLK_SDGMAC_ROOT>; 974 pm_qos = <&qos_fspi1>, 975 <&qos_gmac0>, 976 <&qos_gmac1>, 977 <&qos_sdio>, 978 <&qos_sdmmc>, 979 <&qos_flexbus>; 980 #power-domain-cells = <0>; 981 }; 982 }; 983 984 power-domain@RK3576_PD_PHP { 985 reg = <RK3576_PD_PHP>; 986 clocks = <&cru ACLK_PHP_ROOT>, 987 <&cru PCLK_PHP_ROOT>, 988 <&cru ACLK_MMU0>, 989 <&cru ACLK_MMU1>; 990 pm_qos = <&qos_mmu0>, 991 <&qos_mmu1>; 992 #power-domain-cells = <1>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 power-domain@RK3576_PD_SUBPHP { 997 reg = <RK3576_PD_SUBPHP>; 998 #power-domain-cells = <0>; 999 }; 1000 }; 1001 1002 power-domain@RK3576_PD_AUDIO { 1003 reg = <RK3576_PD_AUDIO>; 1004 #power-domain-cells = <0>; 1005 }; 1006 1007 power-domain@RK3576_PD_VEPU1 { 1008 reg = <RK3576_PD_VEPU1>; 1009 clocks = <&cru ACLK_VEPU1>, 1010 <&cru HCLK_VEPU1>; 1011 pm_qos = <&qos_vepu1>; 1012 #power-domain-cells = <0>; 1013 }; 1014 1015 power-domain@RK3576_PD_VPU { 1016 reg = <RK3576_PD_VPU>; 1017 clocks = <&cru ACLK_EBC>, 1018 <&cru HCLK_EBC>, 1019 <&cru ACLK_JPEG>, 1020 <&cru HCLK_JPEG>, 1021 <&cru ACLK_RGA2E_0>, 1022 <&cru HCLK_RGA2E_0>, 1023 <&cru ACLK_RGA2E_1>, 1024 <&cru HCLK_RGA2E_1>, 1025 <&cru ACLK_VDPP>, 1026 <&cru HCLK_VDPP>; 1027 pm_qos = <&qos_ebc>, 1028 <&qos_jpeg>, 1029 <&qos_rga0>, 1030 <&qos_rga1>, 1031 <&qos_vdpp>; 1032 #power-domain-cells = <0>; 1033 }; 1034 1035 power-domain@RK3576_PD_VDEC { 1036 reg = <RK3576_PD_VDEC>; 1037 clocks = <&cru ACLK_RKVDEC_ROOT>, 1038 <&cru HCLK_RKVDEC>; 1039 pm_qos = <&qos_rkvdec>; 1040 #power-domain-cells = <0>; 1041 }; 1042 1043 power-domain@RK3576_PD_VI { 1044 reg = <RK3576_PD_VI>; 1045 clocks = <&cru ACLK_VICAP>, 1046 <&cru HCLK_VICAP>, 1047 <&cru DCLK_VICAP>, 1048 <&cru ACLK_VI_ROOT>, 1049 <&cru HCLK_VI_ROOT>, 1050 <&cru PCLK_VI_ROOT>, 1051 <&cru CLK_ISP_CORE>, 1052 <&cru ACLK_ISP>, 1053 <&cru HCLK_ISP>, 1054 <&cru CLK_CORE_VPSS>, 1055 <&cru ACLK_VPSS>, 1056 <&cru HCLK_VPSS>; 1057 pm_qos = <&qos_isp_mro>, 1058 <&qos_isp_mwo>, 1059 <&qos_vicap_m0>, 1060 <&qos_vpss_mro>, 1061 <&qos_vpss_mwo>; 1062 #power-domain-cells = <1>; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 power-domain@RK3576_PD_VEPU0 { 1067 reg = <RK3576_PD_VEPU0>; 1068 clocks = <&cru ACLK_VEPU0>, 1069 <&cru HCLK_VEPU0>; 1070 pm_qos = <&qos_vepu0>; 1071 #power-domain-cells = <0>; 1072 }; 1073 }; 1074 1075 power-domain@RK3576_PD_VOP { 1076 reg = <RK3576_PD_VOP>; 1077 clocks = <&cru ACLK_VOP>, 1078 <&cru HCLK_VOP>, 1079 <&cru HCLK_VOP_ROOT>, 1080 <&cru PCLK_VOP_ROOT>; 1081 pm_qos = <&qos_vop_m0>, 1082 <&qos_vop_m1ro>; 1083 #power-domain-cells = <1>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 power-domain@RK3576_PD_USB { 1088 reg = <RK3576_PD_USB>; 1089 clocks = <&cru PCLK_PHP_ROOT>, 1090 <&cru ACLK_USB_ROOT>, 1091 <&cru ACLK_MMU2>, 1092 <&cru ACLK_SLV_MMU2>, 1093 <&cru ACLK_UFS_SYS>; 1094 pm_qos = <&qos_mmu2>, 1095 <&qos_ufshc>; 1096 #power-domain-cells = <0>; 1097 }; 1098 1099 power-domain@RK3576_PD_VO0 { 1100 reg = <RK3576_PD_VO0>; 1101 clocks = <&cru ACLK_HDCP0>, 1102 <&cru HCLK_HDCP0>, 1103 <&cru ACLK_VO0_ROOT>, 1104 <&cru PCLK_VO0_ROOT>, 1105 <&cru HCLK_VOP_ROOT>; 1106 pm_qos = <&qos_hdcp0>; 1107 #power-domain-cells = <0>; 1108 }; 1109 1110 power-domain@RK3576_PD_VO1 { 1111 reg = <RK3576_PD_VO1>; 1112 clocks = <&cru ACLK_HDCP1>, 1113 <&cru HCLK_HDCP1>, 1114 <&cru ACLK_VO1_ROOT>, 1115 <&cru PCLK_VO1_ROOT>, 1116 <&cru HCLK_VOP_ROOT>; 1117 pm_qos = <&qos_hdcp1>; 1118 #power-domain-cells = <0>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 gpu: gpu@27800000 { 1125 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 1126 reg = <0x0 0x27800000 0x0 0x200000>; 1127 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 1128 assigned-clock-rates = <198000000>; 1129 clocks = <&cru CLK_GPU>; 1130 clock-names = "core"; 1131 dynamic-power-coefficient = <1625>; 1132 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "job", "mmu", "gpu"; 1136 operating-points-v2 = <&gpu_opp_table>; 1137 power-domains = <&power RK3576_PD_GPU>; 1138 #cooling-cells = <2>; 1139 status = "disabled"; 1140 }; 1141 1142 vop: vop@27d00000 { 1143 compatible = "rockchip,rk3576-vop"; 1144 reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; 1145 reg-names = "vop", "gamma-lut"; 1146 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1150 interrupt-names = "sys", 1151 "vp0", 1152 "vp1", 1153 "vp2"; 1154 clocks = <&cru ACLK_VOP>, 1155 <&cru HCLK_VOP>, 1156 <&cru DCLK_VP0>, 1157 <&cru DCLK_VP1>, 1158 <&cru DCLK_VP2>, 1159 <&hdptxphy>; 1160 clock-names = "aclk", 1161 "hclk", 1162 "dclk_vp0", 1163 "dclk_vp1", 1164 "dclk_vp2", 1165 "pll_hdmiphy0"; 1166 iommus = <&vop_mmu>; 1167 power-domains = <&power RK3576_PD_VOP>; 1168 rockchip,grf = <&sys_grf>; 1169 rockchip,pmu = <&pmu>; 1170 status = "disabled"; 1171 1172 vop_out: ports { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 vp0: port@0 { 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 reg = <0>; 1180 }; 1181 1182 vp1: port@1 { 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 reg = <1>; 1186 }; 1187 1188 vp2: port@2 { 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 reg = <2>; 1192 }; 1193 }; 1194 }; 1195 1196 vop_mmu: iommu@27d07e00 { 1197 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1198 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 1199 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1201 clock-names = "aclk", "iface"; 1202 #iommu-cells = <0>; 1203 power-domains = <&power RK3576_PD_VOP>; 1204 status = "disabled"; 1205 }; 1206 1207 sai5: sai@27d40000 { 1208 compatible = "rockchip,rk3576-sai"; 1209 reg = <0x0 0x27d40000 0x0 0x1000>; 1210 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 1212 clock-names = "mclk", "hclk"; 1213 dmas = <&dmac2 3>; 1214 dma-names = "rx"; 1215 power-domains = <&power RK3576_PD_VO0>; 1216 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 1217 reset-names = "m", "h"; 1218 rockchip,sai-rx-route = <0 1 2 3>; 1219 #sound-dai-cells = <0>; 1220 sound-name-prefix = "SAI5"; 1221 status = "disabled"; 1222 }; 1223 1224 sai6: sai@27d50000 { 1225 compatible = "rockchip,rk3576-sai"; 1226 reg = <0x0 0x27d50000 0x0 0x1000>; 1227 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 1229 clock-names = "mclk", "hclk"; 1230 dmas = <&dmac2 4>, <&dmac2 5>; 1231 dma-names = "tx", "rx"; 1232 power-domains = <&power RK3576_PD_VO0>; 1233 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 1234 reset-names = "m", "h"; 1235 rockchip,sai-rx-route = <0 1 2 3>; 1236 rockchip,sai-tx-route = <0 1 2 3>; 1237 #sound-dai-cells = <0>; 1238 sound-name-prefix = "SAI6"; 1239 status = "disabled"; 1240 }; 1241 1242 hdmi: hdmi@27da0000 { 1243 compatible = "rockchip,rk3576-dw-hdmi-qp"; 1244 reg = <0x0 0x27da0000 0x0 0x20000>; 1245 clocks = <&cru PCLK_HDMITX0>, 1246 <&cru CLK_HDMITX0_EARC>, 1247 <&cru CLK_HDMITX0_REF>, 1248 <&cru MCLK_SAI6_8CH>, 1249 <&cru CLK_HDMITXHDP>, 1250 <&cru HCLK_VO0_ROOT>; 1251 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1252 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1258 phys = <&hdptxphy>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 1261 power-domains = <&power RK3576_PD_VO0>; 1262 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; 1263 reset-names = "ref", "hdp"; 1264 rockchip,grf = <&ioc_grf>; 1265 rockchip,vo-grf = <&vo0_grf>; 1266 #sound-dai-cells = <0>; 1267 status = "disabled"; 1268 1269 ports { 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 1273 hdmi_in: port@0 { 1274 reg = <0>; 1275 }; 1276 1277 hdmi_out: port@1 { 1278 reg = <1>; 1279 }; 1280 }; 1281 }; 1282 1283 sai7: sai@27ed0000 { 1284 compatible = "rockchip,rk3576-sai"; 1285 reg = <0x0 0x27ed0000 0x0 0x1000>; 1286 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 1288 clock-names = "mclk", "hclk"; 1289 dmas = <&dmac2 19>; 1290 dma-names = "tx"; 1291 power-domains = <&power RK3576_PD_VO1>; 1292 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 1293 reset-names = "m", "h"; 1294 rockchip,sai-tx-route = <0 1 2 3>; 1295 #sound-dai-cells = <0>; 1296 sound-name-prefix = "SAI7"; 1297 status = "disabled"; 1298 }; 1299 1300 sai8: sai@27ee0000 { 1301 compatible = "rockchip,rk3576-sai"; 1302 reg = <0x0 0x27ee0000 0x0 0x1000>; 1303 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 1305 clock-names = "mclk", "hclk"; 1306 dmas = <&dmac1 7>; 1307 dma-names = "tx"; 1308 power-domains = <&power RK3576_PD_VO1>; 1309 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 1310 reset-names = "m", "h"; 1311 rockchip,sai-tx-route = <0 1 2 3>; 1312 #sound-dai-cells = <0>; 1313 sound-name-prefix = "SAI8"; 1314 status = "disabled"; 1315 }; 1316 1317 sai9: sai@27ef0000 { 1318 compatible = "rockchip,rk3576-sai"; 1319 reg = <0x0 0x27ef0000 0x0 0x1000>; 1320 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 1322 clock-names = "mclk", "hclk"; 1323 dmas = <&dmac0 26>; 1324 dma-names = "tx"; 1325 power-domains = <&power RK3576_PD_VO1>; 1326 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 1327 reset-names = "m", "h"; 1328 rockchip,sai-tx-route = <0 1 2 3>; 1329 #sound-dai-cells = <0>; 1330 sound-name-prefix = "SAI9"; 1331 status = "disabled"; 1332 }; 1333 1334 qos_hdcp1: qos@27f02000 { 1335 compatible = "rockchip,rk3576-qos", "syscon"; 1336 reg = <0x0 0x27f02000 0x0 0x20>; 1337 }; 1338 1339 qos_fspi1: qos@27f04000 { 1340 compatible = "rockchip,rk3576-qos", "syscon"; 1341 reg = <0x0 0x27f04000 0x0 0x20>; 1342 }; 1343 1344 qos_gmac0: qos@27f04080 { 1345 compatible = "rockchip,rk3576-qos", "syscon"; 1346 reg = <0x0 0x27f04080 0x0 0x20>; 1347 }; 1348 1349 qos_gmac1: qos@27f04100 { 1350 compatible = "rockchip,rk3576-qos", "syscon"; 1351 reg = <0x0 0x27f04100 0x0 0x20>; 1352 }; 1353 1354 qos_sdio: qos@27f04180 { 1355 compatible = "rockchip,rk3576-qos", "syscon"; 1356 reg = <0x0 0x27f04180 0x0 0x20>; 1357 }; 1358 1359 qos_sdmmc: qos@27f04200 { 1360 compatible = "rockchip,rk3576-qos", "syscon"; 1361 reg = <0x0 0x27f04200 0x0 0x20>; 1362 }; 1363 1364 qos_flexbus: qos@27f04280 { 1365 compatible = "rockchip,rk3576-qos", "syscon"; 1366 reg = <0x0 0x27f04280 0x0 0x20>; 1367 }; 1368 1369 qos_gpu: qos@27f05000 { 1370 compatible = "rockchip,rk3576-qos", "syscon"; 1371 reg = <0x0 0x27f05000 0x0 0x20>; 1372 }; 1373 1374 qos_vepu1: qos@27f06000 { 1375 compatible = "rockchip,rk3576-qos", "syscon"; 1376 reg = <0x0 0x27f06000 0x0 0x20>; 1377 }; 1378 1379 qos_npu_mcu: qos@27f08000 { 1380 compatible = "rockchip,rk3576-qos", "syscon"; 1381 reg = <0x0 0x27f08000 0x0 0x20>; 1382 }; 1383 1384 qos_npu_nsp0: qos@27f08080 { 1385 compatible = "rockchip,rk3576-qos", "syscon"; 1386 reg = <0x0 0x27f08080 0x0 0x20>; 1387 }; 1388 1389 qos_npu_nsp1: qos@27f08100 { 1390 compatible = "rockchip,rk3576-qos", "syscon"; 1391 reg = <0x0 0x27f08100 0x0 0x20>; 1392 }; 1393 1394 qos_emmc: qos@27f09000 { 1395 compatible = "rockchip,rk3576-qos", "syscon"; 1396 reg = <0x0 0x27f09000 0x0 0x20>; 1397 }; 1398 1399 qos_fspi0: qos@27f09080 { 1400 compatible = "rockchip,rk3576-qos", "syscon"; 1401 reg = <0x0 0x27f09080 0x0 0x20>; 1402 }; 1403 1404 qos_mmu0: qos@27f0a000 { 1405 compatible = "rockchip,rk3576-qos", "syscon"; 1406 reg = <0x0 0x27f0a000 0x0 0x20>; 1407 }; 1408 1409 qos_mmu1: qos@27f0a080 { 1410 compatible = "rockchip,rk3576-qos", "syscon"; 1411 reg = <0x0 0x27f0a080 0x0 0x20>; 1412 }; 1413 1414 qos_rkvdec: qos@27f0c000 { 1415 compatible = "rockchip,rk3576-qos", "syscon"; 1416 reg = <0x0 0x27f0c000 0x0 0x20>; 1417 }; 1418 1419 qos_crypto: qos@27f0d000 { 1420 compatible = "rockchip,rk3576-qos", "syscon"; 1421 reg = <0x0 0x27f0d000 0x0 0x20>; 1422 }; 1423 1424 qos_mmu2: qos@27f0e000 { 1425 compatible = "rockchip,rk3576-qos", "syscon"; 1426 reg = <0x0 0x27f0e000 0x0 0x20>; 1427 }; 1428 1429 qos_ufshc: qos@27f0e080 { 1430 compatible = "rockchip,rk3576-qos", "syscon"; 1431 reg = <0x0 0x27f0e080 0x0 0x20>; 1432 }; 1433 1434 qos_vepu0: qos@27f0f000 { 1435 compatible = "rockchip,rk3576-qos", "syscon"; 1436 reg = <0x0 0x27f0f000 0x0 0x20>; 1437 }; 1438 1439 qos_isp_mro: qos@27f10000 { 1440 compatible = "rockchip,rk3576-qos", "syscon"; 1441 reg = <0x0 0x27f10000 0x0 0x20>; 1442 }; 1443 1444 qos_isp_mwo: qos@27f10080 { 1445 compatible = "rockchip,rk3576-qos", "syscon"; 1446 reg = <0x0 0x27f10080 0x0 0x20>; 1447 }; 1448 1449 qos_vicap_m0: qos@27f10100 { 1450 compatible = "rockchip,rk3576-qos", "syscon"; 1451 reg = <0x0 0x27f10100 0x0 0x20>; 1452 }; 1453 1454 qos_vpss_mro: qos@27f10180 { 1455 compatible = "rockchip,rk3576-qos", "syscon"; 1456 reg = <0x0 0x27f10180 0x0 0x20>; 1457 }; 1458 1459 qos_vpss_mwo: qos@27f10200 { 1460 compatible = "rockchip,rk3576-qos", "syscon"; 1461 reg = <0x0 0x27f10200 0x0 0x20>; 1462 }; 1463 1464 qos_hdcp0: qos@27f11000 { 1465 compatible = "rockchip,rk3576-qos", "syscon"; 1466 reg = <0x0 0x27f11000 0x0 0x20>; 1467 }; 1468 1469 qos_vop_m0: qos@27f12800 { 1470 compatible = "rockchip,rk3576-qos", "syscon"; 1471 reg = <0x0 0x27f12800 0x0 0x20>; 1472 }; 1473 1474 qos_vop_m1ro: qos@27f12880 { 1475 compatible = "rockchip,rk3576-qos", "syscon"; 1476 reg = <0x0 0x27f12880 0x0 0x20>; 1477 }; 1478 1479 qos_ebc: qos@27f13000 { 1480 compatible = "rockchip,rk3576-qos", "syscon"; 1481 reg = <0x0 0x27f13000 0x0 0x20>; 1482 }; 1483 1484 qos_rga0: qos@27f13080 { 1485 compatible = "rockchip,rk3576-qos", "syscon"; 1486 reg = <0x0 0x27f13080 0x0 0x20>; 1487 }; 1488 1489 qos_rga1: qos@27f13100 { 1490 compatible = "rockchip,rk3576-qos", "syscon"; 1491 reg = <0x0 0x27f13100 0x0 0x20>; 1492 }; 1493 1494 qos_jpeg: qos@27f13180 { 1495 compatible = "rockchip,rk3576-qos", "syscon"; 1496 reg = <0x0 0x27f13180 0x0 0x20>; 1497 }; 1498 1499 qos_vdpp: qos@27f13200 { 1500 compatible = "rockchip,rk3576-qos", "syscon"; 1501 reg = <0x0 0x27f13200 0x0 0x20>; 1502 }; 1503 1504 qos_npu_m0: qos@27f20000 { 1505 compatible = "rockchip,rk3576-qos", "syscon"; 1506 reg = <0x0 0x27f20000 0x0 0x20>; 1507 }; 1508 1509 qos_npu_m1: qos@27f21000 { 1510 compatible = "rockchip,rk3576-qos", "syscon"; 1511 reg = <0x0 0x27f21000 0x0 0x20>; 1512 }; 1513 1514 qos_npu_m0ro: qos@27f22080 { 1515 compatible = "rockchip,rk3576-qos", "syscon"; 1516 reg = <0x0 0x27f22080 0x0 0x20>; 1517 }; 1518 1519 qos_npu_m1ro: qos@27f22100 { 1520 compatible = "rockchip,rk3576-qos", "syscon"; 1521 reg = <0x0 0x27f22100 0x0 0x20>; 1522 }; 1523 1524 gmac0: ethernet@2a220000 { 1525 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1526 reg = <0x0 0x2a220000 0x0 0x10000>; 1527 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1528 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1529 <&cru CLK_GMAC0_PTP_REF>; 1530 clock-names = "stmmaceth", "clk_mac_ref", 1531 "pclk_mac", "aclk_mac", 1532 "ptp_ref"; 1533 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1535 interrupt-names = "macirq", "eth_wake_irq"; 1536 power-domains = <&power RK3576_PD_SDGMAC>; 1537 resets = <&cru SRST_A_GMAC0>; 1538 reset-names = "stmmaceth"; 1539 rockchip,grf = <&sdgmac_grf>; 1540 rockchip,php-grf = <&ioc_grf>; 1541 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1542 snps,mixed-burst; 1543 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1544 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1545 snps,tso; 1546 status = "disabled"; 1547 1548 mdio0: mdio { 1549 compatible = "snps,dwmac-mdio"; 1550 #address-cells = <0x1>; 1551 #size-cells = <0x0>; 1552 }; 1553 1554 gmac0_stmmac_axi_setup: stmmac-axi-config { 1555 snps,blen = <0 0 0 0 16 8 4>; 1556 snps,rd_osr_lmt = <8>; 1557 snps,wr_osr_lmt = <4>; 1558 }; 1559 1560 gmac0_mtl_rx_setup: rx-queues-config { 1561 snps,rx-queues-to-use = <1>; 1562 queue0 {}; 1563 }; 1564 1565 gmac0_mtl_tx_setup: tx-queues-config { 1566 snps,tx-queues-to-use = <1>; 1567 queue0 {}; 1568 }; 1569 }; 1570 1571 gmac1: ethernet@2a230000 { 1572 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1573 reg = <0x0 0x2a230000 0x0 0x10000>; 1574 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1575 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1576 <&cru CLK_GMAC1_PTP_REF>; 1577 clock-names = "stmmaceth", "clk_mac_ref", 1578 "pclk_mac", "aclk_mac", 1579 "ptp_ref"; 1580 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1582 interrupt-names = "macirq", "eth_wake_irq"; 1583 power-domains = <&power RK3576_PD_SDGMAC>; 1584 resets = <&cru SRST_A_GMAC1>; 1585 reset-names = "stmmaceth"; 1586 rockchip,grf = <&sdgmac_grf>; 1587 rockchip,php-grf = <&ioc_grf>; 1588 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1589 snps,mixed-burst; 1590 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1591 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1592 snps,tso; 1593 status = "disabled"; 1594 1595 mdio1: mdio { 1596 compatible = "snps,dwmac-mdio"; 1597 #address-cells = <0x1>; 1598 #size-cells = <0x0>; 1599 }; 1600 1601 gmac1_stmmac_axi_setup: stmmac-axi-config { 1602 snps,blen = <0 0 0 0 16 8 4>; 1603 snps,rd_osr_lmt = <8>; 1604 snps,wr_osr_lmt = <4>; 1605 }; 1606 1607 gmac1_mtl_rx_setup: rx-queues-config { 1608 snps,rx-queues-to-use = <1>; 1609 queue0 {}; 1610 }; 1611 1612 gmac1_mtl_tx_setup: tx-queues-config { 1613 snps,tx-queues-to-use = <1>; 1614 queue0 {}; 1615 }; 1616 }; 1617 1618 sata0: sata@2a240000 { 1619 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1620 reg = <0x0 0x2a240000 0x0 0x1000>; 1621 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1622 <&cru CLK_RXOOB0>; 1623 clock-names = "sata", "pmalive", "rxoob"; 1624 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1625 power-domains = <&power RK3576_PD_SUBPHP>; 1626 phys = <&combphy0_ps PHY_TYPE_SATA>; 1627 phy-names = "sata-phy"; 1628 ports-implemented = <0x1>; 1629 dma-coherent; 1630 status = "disabled"; 1631 }; 1632 1633 sata1: sata@2a250000 { 1634 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1635 reg = <0x0 0x2a250000 0x0 0x1000>; 1636 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 1637 <&cru CLK_RXOOB1>; 1638 clock-names = "sata", "pmalive", "rxoob"; 1639 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1640 power-domains = <&power RK3576_PD_SUBPHP>; 1641 phys = <&combphy1_psu PHY_TYPE_SATA>; 1642 phy-names = "sata-phy"; 1643 ports-implemented = <0x1>; 1644 dma-coherent; 1645 status = "disabled"; 1646 }; 1647 1648 ufshc: ufshc@2a2d0000 { 1649 compatible = "rockchip,rk3576-ufshc"; 1650 reg = <0x0 0x2a2d0000 0x0 0x10000>, 1651 <0x0 0x2b040000 0x0 0x10000>, 1652 <0x0 0x2601f000 0x0 0x1000>, 1653 <0x0 0x2603c000 0x0 0x1000>, 1654 <0x0 0x2a2e0000 0x0 0x10000>; 1655 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 1656 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 1657 <&cru CLK_REF_UFS_CLKOUT>; 1658 clock-names = "core", "pclk", "pclk_mphy", "ref_out"; 1659 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 1660 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 1661 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1662 power-domains = <&power RK3576_PD_USB>; 1663 pinctrl-0 = <&ufs_refclk>; 1664 pinctrl-names = "default"; 1665 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, 1666 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; 1667 reset-names = "biu", "sys", "ufs", "grf"; 1668 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; 1669 status = "disabled"; 1670 }; 1671 1672 sfc1: spi@2a300000 { 1673 compatible = "rockchip,sfc"; 1674 reg = <0x0 0x2a300000 0x0 0x4000>; 1675 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1676 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 1677 clock-names = "clk_sfc", "hclk_sfc"; 1678 power-domains = <&power RK3576_PD_SDGMAC>; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 status = "disabled"; 1682 }; 1683 1684 sdmmc: mmc@2a310000 { 1685 compatible = "rockchip,rk3576-dw-mshc"; 1686 reg = <0x0 0x2a310000 0x0 0x4000>; 1687 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1688 clock-names = "biu", "ciu"; 1689 fifo-depth = <0x100>; 1690 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1691 max-frequency = <200000000>; 1692 pinctrl-names = "default"; 1693 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1694 power-domains = <&power RK3576_PD_SDGMAC>; 1695 resets = <&cru SRST_H_SDMMC0>; 1696 reset-names = "reset"; 1697 status = "disabled"; 1698 }; 1699 1700 sdio: mmc@2a320000 { 1701 compatible = "rockchip,rk3576-dw-mshc"; 1702 reg = <0x0 0x2a320000 0x0 0x4000>; 1703 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 1704 clock-names = "biu", "ciu"; 1705 fifo-depth = <0x100>; 1706 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1707 max-frequency = <200000000>; 1708 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 1709 pinctrl-names = "default"; 1710 power-domains = <&power RK3576_PD_SDGMAC>; 1711 resets = <&cru SRST_H_SDIO>; 1712 reset-names = "reset"; 1713 status = "disabled"; 1714 }; 1715 1716 sdhci: mmc@2a330000 { 1717 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1718 reg = <0x0 0x2a330000 0x0 0x10000>; 1719 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1720 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1721 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1722 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1723 <&cru TCLK_EMMC>; 1724 clock-names = "core", "bus", "axi", "block", "timer"; 1725 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1726 max-frequency = <200000000>; 1727 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1728 <&emmc_cmd>, <&emmc_strb>; 1729 pinctrl-names = "default"; 1730 power-domains = <&power RK3576_PD_NVM>; 1731 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1732 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1733 <&cru SRST_T_EMMC>; 1734 reset-names = "core", "bus", "axi", "block", "timer"; 1735 supports-cqe; 1736 status = "disabled"; 1737 }; 1738 1739 sfc0: spi@2a340000 { 1740 compatible = "rockchip,sfc"; 1741 reg = <0x0 0x2a340000 0x0 0x4000>; 1742 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1743 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 1744 clock-names = "clk_sfc", "hclk_sfc"; 1745 power-domains = <&power RK3576_PD_NVM>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 status = "disabled"; 1749 }; 1750 1751 rng: rng@2a410000 { 1752 compatible = "rockchip,rk3576-rng"; 1753 reg = <0x0 0x2a410000 0x0 0x200>; 1754 clocks = <&cru HCLK_TRNG_NS>; 1755 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1756 resets = <&cru SRST_H_TRNG_NS>; 1757 }; 1758 1759 otp: otp@2a580000 { 1760 compatible = "rockchip,rk3576-otp"; 1761 reg = <0x0 0x2a580000 0x0 0x400>; 1762 #address-cells = <1>; 1763 #size-cells = <1>; 1764 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1765 <&cru CLK_OTP_PHY_G>; 1766 clock-names = "otp", "apb_pclk", "phy"; 1767 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 1768 reset-names = "otp", "apb"; 1769 1770 /* Data cells */ 1771 cpu_code: cpu-code@2 { 1772 reg = <0x02 0x2>; 1773 }; 1774 otp_cpu_version: cpu-version@5 { 1775 reg = <0x05 0x1>; 1776 bits = <3 3>; 1777 }; 1778 otp_id: id@a { 1779 reg = <0x0a 0x10>; 1780 }; 1781 cpub_leakage: cpub-leakage@1e { 1782 reg = <0x1e 0x1>; 1783 }; 1784 cpul_leakage: cpul-leakage@1f { 1785 reg = <0x1f 0x1>; 1786 }; 1787 npu_leakage: npu-leakage@20 { 1788 reg = <0x20 0x1>; 1789 }; 1790 gpu_leakage: gpu-leakage@21 { 1791 reg = <0x21 0x1>; 1792 }; 1793 log_leakage: log-leakage@22 { 1794 reg = <0x22 0x1>; 1795 }; 1796 }; 1797 1798 sai0: sai@2a600000 { 1799 compatible = "rockchip,rk3576-sai"; 1800 reg = <0x0 0x2a600000 0x0 0x1000>; 1801 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1802 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 1803 clock-names = "mclk", "hclk"; 1804 dmas = <&dmac0 0>, <&dmac0 1>; 1805 dma-names = "tx", "rx"; 1806 power-domains = <&power RK3576_PD_AUDIO>; 1807 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 1808 reset-names = "m", "h"; 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&sai0m0_lrck 1811 &sai0m0_sclk 1812 &sai0m0_sdi0 1813 &sai0m0_sdi1 1814 &sai0m0_sdi2 1815 &sai0m0_sdi3 1816 &sai0m0_sdo0 1817 &sai0m0_sdo1 1818 &sai0m0_sdo2 1819 &sai0m0_sdo3>; 1820 #sound-dai-cells = <0>; 1821 sound-name-prefix = "SAI0"; 1822 status = "disabled"; 1823 }; 1824 1825 sai1: sai@2a610000 { 1826 compatible = "rockchip,rk3576-sai"; 1827 reg = <0x0 0x2a610000 0x0 0x1000>; 1828 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1829 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 1830 clock-names = "mclk", "hclk"; 1831 dmas = <&dmac0 2>, <&dmac0 3>; 1832 dma-names = "tx", "rx"; 1833 power-domains = <&power RK3576_PD_AUDIO>; 1834 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 1835 reset-names = "m", "h"; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&sai1m0_lrck 1838 &sai1m0_sclk 1839 &sai1m0_sdi0 1840 &sai1m0_sdo0 1841 &sai1m0_sdo1 1842 &sai1m0_sdo2 1843 &sai1m0_sdo3>; 1844 #sound-dai-cells = <0>; 1845 sound-name-prefix = "SAI1"; 1846 status = "disabled"; 1847 }; 1848 1849 sai2: sai@2a620000 { 1850 compatible = "rockchip,rk3576-sai"; 1851 reg = <0x0 0x2a620000 0x0 0x1000>; 1852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 1854 clock-names = "mclk", "hclk"; 1855 dmas = <&dmac1 0>, <&dmac1 1>; 1856 dma-names = "tx", "rx"; 1857 power-domains = <&power RK3576_PD_AUDIO>; 1858 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 1859 reset-names = "m", "h"; 1860 pinctrl-names = "default"; 1861 pinctrl-0 = <&sai2m0_lrck 1862 &sai2m0_sclk 1863 &sai2m0_sdi 1864 &sai2m0_sdo>; 1865 #sound-dai-cells = <0>; 1866 sound-name-prefix = "SAI2"; 1867 status = "disabled"; 1868 }; 1869 1870 sai3: sai@2a630000 { 1871 compatible = "rockchip,rk3576-sai"; 1872 reg = <0x0 0x2a630000 0x0 0x1000>; 1873 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 1875 clock-names = "mclk", "hclk"; 1876 dmas = <&dmac1 2>, <&dmac1 3>; 1877 dma-names = "tx", "rx"; 1878 power-domains = <&power RK3576_PD_AUDIO>; 1879 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 1880 reset-names = "m", "h"; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&sai3m0_lrck 1883 &sai3m0_sclk 1884 &sai3m0_sdi 1885 &sai3m0_sdo>; 1886 #sound-dai-cells = <0>; 1887 sound-name-prefix = "SAI3"; 1888 status = "disabled"; 1889 }; 1890 1891 sai4: sai@2a640000 { 1892 compatible = "rockchip,rk3576-sai"; 1893 reg = <0x0 0x2a640000 0x0 0x1000>; 1894 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 1896 clock-names = "mclk", "hclk"; 1897 dmas = <&dmac2 0>, <&dmac2 1>; 1898 dma-names = "tx", "rx"; 1899 power-domains = <&power RK3576_PD_AUDIO>; 1900 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 1901 reset-names = "m", "h"; 1902 pinctrl-names = "default"; 1903 pinctrl-0 = <&sai4m0_lrck 1904 &sai4m0_sclk 1905 &sai4m0_sdi 1906 &sai4m0_sdo>; 1907 #sound-dai-cells = <0>; 1908 sound-name-prefix = "SAI4"; 1909 status = "disabled"; 1910 }; 1911 1912 gic: interrupt-controller@2a701000 { 1913 compatible = "arm,gic-400"; 1914 reg = <0x0 0x2a701000 0 0x10000>, 1915 <0x0 0x2a702000 0 0x10000>, 1916 <0x0 0x2a704000 0 0x10000>, 1917 <0x0 0x2a706000 0 0x10000>; 1918 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1919 interrupt-controller; 1920 #interrupt-cells = <3>; 1921 #address-cells = <2>; 1922 #size-cells = <2>; 1923 }; 1924 1925 dmac0: dma-controller@2ab90000 { 1926 compatible = "arm,pl330", "arm,primecell"; 1927 reg = <0x0 0x2ab90000 0x0 0x4000>; 1928 arm,pl330-periph-burst; 1929 clocks = <&cru ACLK_DMAC0>; 1930 clock-names = "apb_pclk"; 1931 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1933 #dma-cells = <1>; 1934 }; 1935 1936 dmac1: dma-controller@2abb0000 { 1937 compatible = "arm,pl330", "arm,primecell"; 1938 reg = <0x0 0x2abb0000 0x0 0x4000>; 1939 arm,pl330-periph-burst; 1940 clocks = <&cru ACLK_DMAC1>; 1941 clock-names = "apb_pclk"; 1942 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1944 #dma-cells = <1>; 1945 }; 1946 1947 dmac2: dma-controller@2abd0000 { 1948 compatible = "arm,pl330", "arm,primecell"; 1949 reg = <0x0 0x2abd0000 0x0 0x4000>; 1950 arm,pl330-periph-burst; 1951 clocks = <&cru ACLK_DMAC2>; 1952 clock-names = "apb_pclk"; 1953 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1955 #dma-cells = <1>; 1956 }; 1957 1958 i2c1: i2c@2ac40000 { 1959 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1960 reg = <0x0 0x2ac40000 0x0 0x1000>; 1961 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1962 clock-names = "i2c", "pclk"; 1963 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1964 pinctrl-names = "default"; 1965 pinctrl-0 = <&i2c1m0_xfer>; 1966 #address-cells = <1>; 1967 #size-cells = <0>; 1968 status = "disabled"; 1969 }; 1970 1971 i2c2: i2c@2ac50000 { 1972 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1973 reg = <0x0 0x2ac50000 0x0 0x1000>; 1974 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1975 clock-names = "i2c", "pclk"; 1976 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1977 pinctrl-names = "default"; 1978 pinctrl-0 = <&i2c2m0_xfer>; 1979 #address-cells = <1>; 1980 #size-cells = <0>; 1981 status = "disabled"; 1982 }; 1983 1984 i2c3: i2c@2ac60000 { 1985 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1986 reg = <0x0 0x2ac60000 0x0 0x1000>; 1987 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1988 clock-names = "i2c", "pclk"; 1989 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1990 pinctrl-names = "default"; 1991 pinctrl-0 = <&i2c3m0_xfer>; 1992 #address-cells = <1>; 1993 #size-cells = <0>; 1994 status = "disabled"; 1995 }; 1996 1997 i2c4: i2c@2ac70000 { 1998 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1999 reg = <0x0 0x2ac70000 0x0 0x1000>; 2000 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2001 clock-names = "i2c", "pclk"; 2002 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2003 pinctrl-names = "default"; 2004 pinctrl-0 = <&i2c4m0_xfer>; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 status = "disabled"; 2008 }; 2009 2010 i2c5: i2c@2ac80000 { 2011 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2012 reg = <0x0 0x2ac80000 0x0 0x1000>; 2013 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2014 clock-names = "i2c", "pclk"; 2015 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&i2c5m0_xfer>; 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 status = "disabled"; 2021 }; 2022 2023 i2c6: i2c@2ac90000 { 2024 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2025 reg = <0x0 0x2ac90000 0x0 0x1000>; 2026 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2027 clock-names = "i2c", "pclk"; 2028 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2029 pinctrl-names = "default"; 2030 pinctrl-0 = <&i2c6m0_xfer>; 2031 #address-cells = <1>; 2032 #size-cells = <0>; 2033 status = "disabled"; 2034 }; 2035 2036 i2c7: i2c@2aca0000 { 2037 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2038 reg = <0x0 0x2aca0000 0x0 0x1000>; 2039 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2040 clock-names = "i2c", "pclk"; 2041 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2042 pinctrl-names = "default"; 2043 pinctrl-0 = <&i2c7m0_xfer>; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 status = "disabled"; 2047 }; 2048 2049 i2c8: i2c@2acb0000 { 2050 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2051 reg = <0x0 0x2acb0000 0x0 0x1000>; 2052 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2053 clock-names = "i2c", "pclk"; 2054 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2055 pinctrl-names = "default"; 2056 pinctrl-0 = <&i2c8m0_xfer>; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 status = "disabled"; 2060 }; 2061 2062 timer0: timer@2acc0000 { 2063 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 2064 reg = <0x0 0x2acc0000 0x0 0x20>; 2065 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 2066 clock-names = "pclk", "timer"; 2067 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2068 }; 2069 2070 wdt: watchdog@2ace0000 { 2071 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 2072 reg = <0x0 0x2ace0000 0x0 0x100>; 2073 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2074 clock-names = "tclk", "pclk"; 2075 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2076 status = "disabled"; 2077 }; 2078 2079 spi0: spi@2acf0000 { 2080 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2081 reg = <0x0 0x2acf0000 0x0 0x1000>; 2082 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2083 clock-names = "spiclk", "apb_pclk"; 2084 dmas = <&dmac0 14>, <&dmac0 15>; 2085 dma-names = "tx", "rx"; 2086 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2087 num-cs = <2>; 2088 pinctrl-names = "default"; 2089 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 status = "disabled"; 2093 }; 2094 2095 spi1: spi@2ad00000 { 2096 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2097 reg = <0x0 0x2ad00000 0x0 0x1000>; 2098 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2099 clock-names = "spiclk", "apb_pclk"; 2100 dmas = <&dmac0 16>, <&dmac0 17>; 2101 dma-names = "tx", "rx"; 2102 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2103 num-cs = <2>; 2104 pinctrl-names = "default"; 2105 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 status = "disabled"; 2109 }; 2110 2111 spi2: spi@2ad10000 { 2112 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2113 reg = <0x0 0x2ad10000 0x0 0x1000>; 2114 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2115 clock-names = "spiclk", "apb_pclk"; 2116 dmas = <&dmac1 15>, <&dmac1 16>; 2117 dma-names = "tx", "rx"; 2118 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2119 num-cs = <2>; 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 status = "disabled"; 2125 }; 2126 2127 spi3: spi@2ad20000 { 2128 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2129 reg = <0x0 0x2ad20000 0x0 0x1000>; 2130 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2131 clock-names = "spiclk", "apb_pclk"; 2132 dmas = <&dmac1 17>, <&dmac1 18>; 2133 dma-names = "tx", "rx"; 2134 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2135 num-cs = <2>; 2136 pinctrl-names = "default"; 2137 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 status = "disabled"; 2141 }; 2142 2143 spi4: spi@2ad30000 { 2144 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2145 reg = <0x0 0x2ad30000 0x0 0x1000>; 2146 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2147 clock-names = "spiclk", "apb_pclk"; 2148 dmas = <&dmac2 12>, <&dmac2 13>; 2149 dma-names = "tx", "rx"; 2150 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2151 num-cs = <2>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 status = "disabled"; 2157 }; 2158 2159 uart0: serial@2ad40000 { 2160 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2161 reg = <0x0 0x2ad40000 0x0 0x100>; 2162 reg-shift = <2>; 2163 reg-io-width = <4>; 2164 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 2165 clock-names = "baudclk", "apb_pclk"; 2166 dmas = <&dmac0 6>, <&dmac0 7>; 2167 dma-names = "tx", "rx"; 2168 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2169 pinctrl-0 = <&uart0m0_xfer>; 2170 pinctrl-names = "default"; 2171 status = "disabled"; 2172 }; 2173 2174 uart2: serial@2ad50000 { 2175 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2176 reg = <0x0 0x2ad50000 0x0 0x100>; 2177 reg-shift = <2>; 2178 reg-io-width = <4>; 2179 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2180 clock-names = "baudclk", "apb_pclk"; 2181 dmas = <&dmac0 10>, <&dmac0 11>; 2182 dma-names = "tx", "rx"; 2183 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2184 pinctrl-names = "default"; 2185 pinctrl-0 = <&uart2m0_xfer>; 2186 status = "disabled"; 2187 }; 2188 2189 uart3: serial@2ad60000 { 2190 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2191 reg = <0x0 0x2ad60000 0x0 0x100>; 2192 reg-shift = <2>; 2193 reg-io-width = <4>; 2194 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2195 clock-names = "baudclk", "apb_pclk"; 2196 dmas = <&dmac0 12>, <&dmac0 13>; 2197 dma-names = "tx", "rx"; 2198 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2199 pinctrl-0 = <&uart3m0_xfer>; 2200 pinctrl-names = "default"; 2201 status = "disabled"; 2202 }; 2203 2204 uart4: serial@2ad70000 { 2205 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2206 reg = <0x0 0x2ad70000 0x0 0x100>; 2207 reg-shift = <2>; 2208 reg-io-width = <4>; 2209 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2210 clock-names = "baudclk", "apb_pclk"; 2211 dmas = <&dmac1 9>, <&dmac1 10>; 2212 dma-names = "tx", "rx"; 2213 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2214 pinctrl-0 = <&uart4m0_xfer>; 2215 pinctrl-names = "default"; 2216 status = "disabled"; 2217 }; 2218 2219 uart5: serial@2ad80000 { 2220 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2221 reg = <0x0 0x2ad80000 0x0 0x100>; 2222 reg-shift = <2>; 2223 reg-io-width = <4>; 2224 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2225 clock-names = "baudclk", "apb_pclk"; 2226 dmas = <&dmac1 11>, <&dmac1 12>; 2227 dma-names = "tx", "rx"; 2228 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2229 pinctrl-0 = <&uart5m0_xfer>; 2230 pinctrl-names = "default"; 2231 status = "disabled"; 2232 }; 2233 2234 uart6: serial@2ad90000 { 2235 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2236 reg = <0x0 0x2ad90000 0x0 0x100>; 2237 reg-shift = <2>; 2238 reg-io-width = <4>; 2239 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2240 clock-names = "baudclk", "apb_pclk"; 2241 dmas = <&dmac1 13>, <&dmac1 14>; 2242 dma-names = "tx", "rx"; 2243 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2244 pinctrl-0 = <&uart6m0_xfer>; 2245 pinctrl-names = "default"; 2246 status = "disabled"; 2247 }; 2248 2249 uart7: serial@2ada0000 { 2250 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2251 reg = <0x0 0x2ada0000 0x0 0x100>; 2252 reg-shift = <2>; 2253 reg-io-width = <4>; 2254 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2255 clock-names = "baudclk", "apb_pclk"; 2256 dmas = <&dmac2 6>, <&dmac2 7>; 2257 dma-names = "tx", "rx"; 2258 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2259 pinctrl-0 = <&uart7m0_xfer>; 2260 pinctrl-names = "default"; 2261 status = "disabled"; 2262 }; 2263 2264 uart8: serial@2adb0000 { 2265 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2266 reg = <0x0 0x2adb0000 0x0 0x100>; 2267 reg-shift = <2>; 2268 reg-io-width = <4>; 2269 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2270 clock-names = "baudclk", "apb_pclk"; 2271 dmas = <&dmac2 8>, <&dmac2 9>; 2272 dma-names = "tx", "rx"; 2273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 2274 pinctrl-0 = <&uart8m0_xfer>; 2275 pinctrl-names = "default"; 2276 status = "disabled"; 2277 }; 2278 2279 uart9: serial@2adc0000 { 2280 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2281 reg = <0x0 0x2adc0000 0x0 0x100>; 2282 reg-shift = <2>; 2283 reg-io-width = <4>; 2284 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2285 clock-names = "baudclk", "apb_pclk"; 2286 dmas = <&dmac2 10>, <&dmac2 11>; 2287 dma-names = "tx", "rx"; 2288 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2289 pinctrl-0 = <&uart9m0_xfer>; 2290 pinctrl-names = "default"; 2291 status = "disabled"; 2292 }; 2293 2294 saradc: adc@2ae00000 { 2295 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 2296 reg = <0x0 0x2ae00000 0x0 0x10000>; 2297 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2298 clock-names = "saradc", "apb_pclk"; 2299 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2300 resets = <&cru SRST_P_SARADC>; 2301 reset-names = "saradc-apb"; 2302 #io-channel-cells = <1>; 2303 status = "disabled"; 2304 }; 2305 2306 i2c9: i2c@2ae80000 { 2307 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2308 reg = <0x0 0x2ae80000 0x0 0x1000>; 2309 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 2310 clock-names = "i2c", "pclk"; 2311 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2312 pinctrl-names = "default"; 2313 pinctrl-0 = <&i2c9m0_xfer>; 2314 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 2315 reset-names = "i2c", "apb"; 2316 #address-cells = <1>; 2317 #size-cells = <0>; 2318 status = "disabled"; 2319 }; 2320 2321 uart10: serial@2afc0000 { 2322 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2323 reg = <0x0 0x2afc0000 0x0 0x100>; 2324 reg-shift = <2>; 2325 reg-io-width = <4>; 2326 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 2327 clock-names = "baudclk", "apb_pclk"; 2328 dmas = <&dmac2 21>, <&dmac2 22>; 2329 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2330 pinctrl-names = "default"; 2331 pinctrl-0 = <&uart10m0_xfer>; 2332 status = "disabled"; 2333 }; 2334 2335 uart11: serial@2afd0000 { 2336 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2337 reg = <0x0 0x2afd0000 0x0 0x100>; 2338 reg-shift = <2>; 2339 reg-io-width = <4>; 2340 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 2341 clock-names = "baudclk", "apb_pclk"; 2342 dmas = <&dmac2 23>, <&dmac2 24>; 2343 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 2344 pinctrl-names = "default"; 2345 pinctrl-0 = <&uart11m0_xfer>; 2346 status = "disabled"; 2347 }; 2348 2349 combphy0_ps: phy@2b050000 { 2350 compatible = "rockchip,rk3576-naneng-combphy"; 2351 reg = <0x0 0x2b050000 0x0 0x100>; 2352 #phy-cells = <1>; 2353 clocks = <&cru CLK_REF_PCIE0_PHY>, 2354 <&cru PCLK_PCIE2_COMBOPHY0>, 2355 <&cru PCLK_PCIE0>; 2356 clock-names = "ref", "apb", "pipe"; 2357 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 2358 assigned-clock-rates = <100000000>; 2359 resets = <&cru SRST_PCIE0_PIPE_PHY>, 2360 <&cru SRST_P_PCIE2_COMBOPHY0>; 2361 reset-names = "phy", "apb"; 2362 rockchip,pipe-grf = <&php_grf>; 2363 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2364 status = "disabled"; 2365 }; 2366 2367 combphy1_psu: phy@2b060000 { 2368 compatible = "rockchip,rk3576-naneng-combphy"; 2369 reg = <0x0 0x2b060000 0x0 0x100>; 2370 #phy-cells = <1>; 2371 clocks = <&cru CLK_REF_PCIE1_PHY>, 2372 <&cru PCLK_PCIE2_COMBOPHY1>, 2373 <&cru PCLK_PCIE1>; 2374 clock-names = "ref", "apb", "pipe"; 2375 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 2376 assigned-clock-rates = <100000000>; 2377 resets = <&cru SRST_PCIE1_PIPE_PHY>, 2378 <&cru SRST_P_PCIE2_COMBOPHY1>; 2379 reset-names = "phy", "apb"; 2380 rockchip,pipe-grf = <&php_grf>; 2381 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 2382 status = "disabled"; 2383 }; 2384 2385 usbdp_phy: phy@2b010000 { 2386 compatible = "rockchip,rk3576-usbdp-phy"; 2387 reg = <0x0 0x2b010000 0x0 0x10000>; 2388 #phy-cells = <1>; 2389 clocks = <&cru CLK_PHY_REF_SRC >, 2390 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 2391 <&cru PCLK_USBDPPHY>, 2392 <&u2phy0>; 2393 clock-names = "refclk", "immortal", "pclk", "utmi"; 2394 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 2395 <&cru SRST_USBDP_COMBO_PHY_CMN>, 2396 <&cru SRST_USBDP_COMBO_PHY_LANE>, 2397 <&cru SRST_USBDP_COMBO_PHY_PCS>, 2398 <&cru SRST_P_USBDPPHY>; 2399 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2400 rockchip,u2phy-grf = <&usb2phy_grf>; 2401 rockchip,usb-grf = <&usb_grf>; 2402 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 2403 rockchip,vo-grf = <&vo1_grf>; 2404 status = "disabled"; 2405 }; 2406 2407 hdptxphy: hdmiphy@2b000000 { 2408 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 2409 reg = <0x0 0x2b000000 0x0 0x2000>; 2410 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; 2411 clock-names = "ref", "apb"; 2412 #clock-cells = <0>; 2413 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 2414 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 2415 reset-names = "apb", "init", "cmn", "lane"; 2416 rockchip,grf = <&hdptxphy_grf>; 2417 #phy-cells = <0>; 2418 status = "disabled"; 2419 }; 2420 2421 sram: sram@3ff88000 { 2422 compatible = "mmio-sram"; 2423 reg = <0x0 0x3ff88000 0x0 0x78000>; 2424 ranges = <0x0 0x0 0x3ff88000 0x78000>; 2425 #address-cells = <1>; 2426 #size-cells = <1>; 2427 2428 /* start address and size should be 4k align */ 2429 rkvdec_sram: rkvdec-sram@0 { 2430 reg = <0x0 0x78000>; 2431 }; 2432 }; 2433 2434 scmi_shmem: scmi-shmem@4010f000 { 2435 compatible = "arm,scmi-shmem"; 2436 reg = <0x0 0x4010f000 0x0 0x100>; 2437 }; 2438 }; 2439}; 2440 2441#include "rk3576-pinctrl.dtsi" 2442