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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da6xx.xml35 <domain name="A6XX" width="32" prefix="variant" varset="chip">
50 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
162 <reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/>
167 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX">
174 <reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/>
175 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/>
184 …<reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"…
186 <reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/>
199 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/>
200 <reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/>
[all …]
H A Da6xx_gmu.xml8 <domain name="A6XX" width="32" prefix="variant" varset="chip">
98 <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX">
133 <reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/>
135 <reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/>
137 <reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/>
146 <reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
148 <reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>
150 <reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/>
152 <reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/>
/linux/drivers/gpu/drm/msm/
H A DMakefile212 $(eval $(call adreno_perfcntrs,a6xx,a6xx))
213 $(eval $(call adreno_perfcntrs,a7xx,a6xx))
214 $(eval $(call adreno_perfcntrs,a8xx,a6xx))
223 generated/a6xx.xml.h \
H A Dmsm_gpu.h268 * switch-over happened early enough in mesa a6xx bringup that we
269 * can disallow relocs for a6xx and newer.
H A Dmsm_drv.c38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_catalog.c11 #include "a6xx.xml.h"
694 .a6xx = &(const struct a6xx_info) {
725 .a6xx = &(const struct a6xx_info) {
744 .a6xx = &(const struct a6xx_info) {
775 .a6xx = &(const struct a6xx_info) {
801 .a6xx = &(const struct a6xx_info) {
825 .a6xx = &(const struct a6xx_info) {
850 .a6xx = &(const struct a6xx_info) {
875 .a6xx = &(const struct a6xx_info) {
901 .a6xx = &(const struct a6xx_info) {
[all …]
H A Dadreno_gpu.h26 ADRENO_FW_SQE = 0, /* a6xx */
28 ADRENO_FW_GMU = 1, /* a6xx */
122 const struct a6xx_info *a6xx; member
284 * for all a6xx devices, but probably best to limit this in adreno_patchid()
673 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
H A Da8xx_gpu.c89 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a8xx_gpu_get_slice_info()
207 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a8xx_set_hwcg()
238 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a8xx_set_cp_protect()
367 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a8xx_nonctxt_config()
409 reglist = adreno_gpu->info->a6xx->ifpc_reglist; in a8xx_patch_pwrup_reglist()
423 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a8xx_patch_pwrup_reglist()
448 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; in a8xx_patch_pwrup_reglist()
H A Da6xx_gpu.c651 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) in a6xx_set_hwcg()
678 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a6xx_set_hwcg()
684 if (!adreno_gpu->info->a6xx->hwcg) { in a6xx_set_hwcg()
713 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) in a6xx_set_hwcg()
726 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a6xx_set_cp_protect()
823 reglist = adreno_gpu->info->a6xx->ifpc_reglist; in a7xx_patch_pwrup_reglist()
837 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a7xx_patch_pwrup_reglist()
860 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; in a7xx_patch_pwrup_reglist()
1325 if (adreno_gpu->info->a6xx->prim_fifo_threshold) in hw_init()
1327 adreno_gpu->info->a6xx->prim_fifo_threshold); in hw_init()
[all …]
H A Da6xx_gmu.c159 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_set_freq()
934 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; in a6xx_gmu_fw_start()
1358 * Warm boot path does not work on newer A6xx GPUs in a6xx_gmu_resume()
1659 /* GMU on A6xx votes perfmode on all valid bandwidth */ in a6xx_gmu_rpmh_bw_votes_init()
1846 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_rpmh_votes_init()
1945 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_pwrlevels_probe()
H A Da6xx_gpu_state.h10 #include "a6xx.xml.h"
H A Da6xx_hfi.c804 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_hfi_send_bw_table()
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml105 For a5xx and a6xx devices this node contains a memory-region that
457 then: # Starting with A6xx, the clocks are usually defined in the GMU node
514 // Example a6xx (with GMU):
H A Dgmu.yaml16 to members of the Adreno A6xx GPU family. The GMU provides on-device power