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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Dadreno_common.xml11 <value name="A5XX" value="5"/>
365 <doc>Address mode for a5xx+</doc>
372 Line mode for a5xx+
H A Da6xx.xml765 Compared to a5xx and earlier, we just program the address of the first
1587 Compared to a5xx and before, we configure both a GMEM base and
1763 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
1913 <!-- unlike a5xx, these are per channel values rather than packed -->
2637 Starting with a5xx, position/psize outputs from shader end up in the
3303 <!-- looks to work in the same way as a5xx: -->
3329 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
H A Da5xx.xml815 <domain name="A5XX" width="32">
2504 Starting with a5xx, position/psize outputs from shader end up in the
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.h13 #include "a5xx.xml.h"
H A Da5xx_gpu.c1637 /* Dump the additional a5xx HLSQ registers */ in a5xx_show()