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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Dadreno_common.xml11 <value name="A5XX" value="5"/>
365 <doc>Address mode for a5xx+</doc>
372 Line mode for a5xx+
H A Da6xx.xml23 <!-- these might be same as a5xx -->
188 <!-- probably same as a5xx -->
2965 Compared to a5xx and earlier, we just program the address of the first
3664 Compared to a5xx and before, we configure both a GMEM base and
3838 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
3983 <!-- unlike a5xx, these are per channel values rather than packed -->
4680 Starting with a5xx, position/psize outputs from shader end up in the
5322 <!-- looks to work in the same way as a5xx: -->
5335 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
5812 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
H A Da5xx.xml815 <domain name="A5XX" width="32">
2504 Starting with a5xx, position/psize outputs from shader end up in the
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_catalog.c152 DECLARE_ADRENO_GPULIST(a5xx);
H A Da5xx_gpu.h13 #include "a5xx.xml.h"
H A Dadreno_gpu.h635 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
H A Da5xx_gpu.c1635 /* Dump the additional a5xx HLSQ registers */ in a5xx_show()
1799 /* a5xx only supports UBWC 1.0, these are not configurable */ in a5xx_gpu_init()
/linux/drivers/gpu/drm/msm/
H A DMakefile197 generated/a5xx.xml.h \
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml109 For a5xx and a6xx devices this node contains a memory-region that