Searched full:a5xx (Results 1 – 9 of 9) sorted by relevance
9 <value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>10 <value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>11 <value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>12 <value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->49 <value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/>52 <!-- a5xx events -->53 <value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>54 <value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>55 <value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>[all …]
11 <value name="A5XX" value="5"/>366 <doc>Address mode for a5xx+</doc>373 Line mode for a5xx+
177 <!-- probably same as a5xx -->
1361 Compared to a5xx and earlier, we just program the address of the first2375 Compared to a5xx and before, we configure both a GMEM base and2569 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->2749 <!-- unlike a5xx, these are per channel values rather than packed -->3620 Starting with a5xx, position/psize outputs from shader end up in the4362 <!-- looks to work in the same way as a5xx: -->4394 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
815 <domain name="A5XX" width="32">2504 Starting with a5xx, position/psize outputs from shader end up in the
153 DECLARE_ADRENO_GPULIST(a5xx);
13 #include "a5xx.xml.h"
669 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
1636 /* Dump the additional a5xx HLSQ registers */ in a5xx_show()