Searched full:a3xx (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a3xx_gpu.h | 16 #include "a3xx.xml.h"
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| H A D | a3xx_catalog.c | 88 DECLARE_ADRENO_GPULIST(a3xx);
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| H A D | a3xx_gpu.c | 312 * for a2xx and a3xx.. we could possibly push that part down to in a3xx_hw_init() 552 DRM_DEV_ERROR(dev->dev, "no a3xx device\n"); in a3xx_gpu_init()
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| /linux/drivers/gpu/drm/msm/registers/ |
| H A D | freedreno_copyright.xml | 13 many a3xx/a4xx contributions
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| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_ringbuffer.h | 130 /* ringbuffer helpers (the parts that are same for a3xx/a2xx/z180..) */
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| H A D | NOTES | 16 + and either a2xx or a3xx 3d core.
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| H A D | Makefile | 220 generated/a3xx.xml.h \
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| H A D | msm_gpu.h | 37 * + a3xx or a2xx 3d core, which share a common CP (the firmware
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | gpu.yaml | 90 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 465 // Example a3xx/4xx:
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| /linux/drivers/gpu/drm/msm/registers/adreno/ |
| H A D | a4xx.xml | 70 <!-- hmm, shifted one compared to a3xx?!? --> 337 on a3xx the countable #'s from AMD_performance_monitor disagreed with 342 <!-- first ctr at least seems same as a3xx, so we can measure freq --> 936 common value is 2, like on a3xx.. 1661 <!-- TODO double check.. for now assume same as a3xx --> 2032 <!-- I guess same as a3xx, but so far only seen 08000050 --> 2368 like a3xx we seem to have two LAYERSZ's.. although this one
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| H A D | a6xx.xml | 1429 <!-- guess based on a3xx and meaning of bits 8 and 9 1723 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 1730 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 1736 <!-- I'm guessing this is the same as a3xx --> 3706 Seems to be the same as a3xx. The maximum stack 3710 size of the PC? a3xx docs say it's 16 bits 3763 a3xx. The ldp/stp offset formula above isn't affected by 4249 This enum is probably similar in purpose to SNORMMODE on a3xx, 4653 A3xx field, except that it's not necessary to set it to anything but the maximum, since
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| H A D | a2xx.xml | 1050 any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where 1052 register on a3xx.. so moving this back into A2XX domain:
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| H A D | a3xx.xml | 558 <domain name="A3XX" width="32"> 633 to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
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