xref: /linux/arch/riscv/kernel/cpufeature.c (revision 2a1944bff54907a4e68f167dcdf772b1e4c3ce6d)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copied from arch/arm64/kernel/cpufeature.c
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  * Copyright (C) 2017 SiFive
7  */
8 
9 #include <linux/acpi.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/ctype.h>
14 #include <linux/log2.h>
15 #include <linux/memory.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <asm/acpi.h>
19 #include <asm/alternative.h>
20 #include <asm/bugs.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cpufeature.h>
23 #include <asm/hwcap.h>
24 #include <asm/text-patching.h>
25 #include <asm/hwprobe.h>
26 #include <asm/processor.h>
27 #include <asm/sbi.h>
28 #include <asm/vector.h>
29 #include <asm/vendor_extensions.h>
30 #include <asm/vendor_extensions/thead.h>
31 
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 
34 static bool any_cpu_has_zicboz;
35 
36 unsigned long elf_hwcap __read_mostly;
37 
38 /* Host ISA bitmap */
39 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
40 
41 /* Per-cpu ISA extensions. */
42 struct riscv_isainfo hart_isa[NR_CPUS];
43 
44 u32 thead_vlenb_of;
45 
46 /**
47  * riscv_isa_extension_base() - Get base extension word
48  *
49  * @isa_bitmap: ISA bitmap to use
50  * Return: base extension word as unsigned long value
51  *
52  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
53  */
riscv_isa_extension_base(const unsigned long * isa_bitmap)54 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
55 {
56 	if (!isa_bitmap)
57 		return riscv_isa[0];
58 	return isa_bitmap[0];
59 }
60 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
61 
62 /**
63  * __riscv_isa_extension_available() - Check whether given extension
64  * is available or not
65  *
66  * @isa_bitmap: ISA bitmap to use
67  * @bit: bit position of the desired extension
68  * Return: true or false
69  *
70  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
71  */
__riscv_isa_extension_available(const unsigned long * isa_bitmap,unsigned int bit)72 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
73 {
74 	const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
75 
76 	if (bit >= RISCV_ISA_EXT_MAX)
77 		return false;
78 
79 	return test_bit(bit, bmap) ? true : false;
80 }
81 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
82 
riscv_ext_zicbom_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)83 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
84 				     const unsigned long *isa_bitmap)
85 {
86 	if (!riscv_cbom_block_size) {
87 		pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
88 		return -EINVAL;
89 	}
90 	if (!is_power_of_2(riscv_cbom_block_size)) {
91 		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
92 		return -EINVAL;
93 	}
94 	return 0;
95 }
96 
riscv_ext_zicboz_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)97 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
98 				     const unsigned long *isa_bitmap)
99 {
100 	if (!riscv_cboz_block_size) {
101 		pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
102 		return -EINVAL;
103 	}
104 	if (!is_power_of_2(riscv_cboz_block_size)) {
105 		pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
106 		return -EINVAL;
107 	}
108 	any_cpu_has_zicboz = true;
109 	return 0;
110 }
111 
riscv_ext_zca_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)112 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
113 				 const unsigned long *isa_bitmap)
114 {
115 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
116 		return 0;
117 
118 	return -EPROBE_DEFER;
119 }
riscv_ext_zcd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)120 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
121 				  const unsigned long *isa_bitmap)
122 {
123 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
124 	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
125 		return 0;
126 
127 	return -EPROBE_DEFER;
128 }
129 
riscv_ext_zcf_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)130 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
131 				  const unsigned long *isa_bitmap)
132 {
133 	if (IS_ENABLED(CONFIG_64BIT))
134 		return -EINVAL;
135 
136 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
137 	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
138 		return 0;
139 
140 	return -EPROBE_DEFER;
141 }
142 
riscv_ext_svadu_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)143 static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
144 				    const unsigned long *isa_bitmap)
145 {
146 	/* SVADE has already been detected, use SVADE only */
147 	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
148 		return -EOPNOTSUPP;
149 
150 	return 0;
151 }
152 
153 static const unsigned int riscv_zk_bundled_exts[] = {
154 	RISCV_ISA_EXT_ZBKB,
155 	RISCV_ISA_EXT_ZBKC,
156 	RISCV_ISA_EXT_ZBKX,
157 	RISCV_ISA_EXT_ZKND,
158 	RISCV_ISA_EXT_ZKNE,
159 	RISCV_ISA_EXT_ZKR,
160 	RISCV_ISA_EXT_ZKT,
161 };
162 
163 static const unsigned int riscv_zkn_bundled_exts[] = {
164 	RISCV_ISA_EXT_ZBKB,
165 	RISCV_ISA_EXT_ZBKC,
166 	RISCV_ISA_EXT_ZBKX,
167 	RISCV_ISA_EXT_ZKND,
168 	RISCV_ISA_EXT_ZKNE,
169 	RISCV_ISA_EXT_ZKNH,
170 };
171 
172 static const unsigned int riscv_zks_bundled_exts[] = {
173 	RISCV_ISA_EXT_ZBKB,
174 	RISCV_ISA_EXT_ZBKC,
175 	RISCV_ISA_EXT_ZKSED,
176 	RISCV_ISA_EXT_ZKSH
177 };
178 
179 #define RISCV_ISA_EXT_ZVKN	\
180 	RISCV_ISA_EXT_ZVKNED,	\
181 	RISCV_ISA_EXT_ZVKNHB,	\
182 	RISCV_ISA_EXT_ZVKB,	\
183 	RISCV_ISA_EXT_ZVKT
184 
185 static const unsigned int riscv_zvkn_bundled_exts[] = {
186 	RISCV_ISA_EXT_ZVKN
187 };
188 
189 static const unsigned int riscv_zvknc_bundled_exts[] = {
190 	RISCV_ISA_EXT_ZVKN,
191 	RISCV_ISA_EXT_ZVBC
192 };
193 
194 static const unsigned int riscv_zvkng_bundled_exts[] = {
195 	RISCV_ISA_EXT_ZVKN,
196 	RISCV_ISA_EXT_ZVKG
197 };
198 
199 #define RISCV_ISA_EXT_ZVKS	\
200 	RISCV_ISA_EXT_ZVKSED,	\
201 	RISCV_ISA_EXT_ZVKSH,	\
202 	RISCV_ISA_EXT_ZVKB,	\
203 	RISCV_ISA_EXT_ZVKT
204 
205 static const unsigned int riscv_zvks_bundled_exts[] = {
206 	RISCV_ISA_EXT_ZVKS
207 };
208 
209 static const unsigned int riscv_zvksc_bundled_exts[] = {
210 	RISCV_ISA_EXT_ZVKS,
211 	RISCV_ISA_EXT_ZVBC
212 };
213 
214 static const unsigned int riscv_zvksg_bundled_exts[] = {
215 	RISCV_ISA_EXT_ZVKS,
216 	RISCV_ISA_EXT_ZVKG
217 };
218 
219 static const unsigned int riscv_zvbb_exts[] = {
220 	RISCV_ISA_EXT_ZVKB
221 };
222 
223 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
224 	RISCV_ISA_EXT_ZVE64X,		\
225 	RISCV_ISA_EXT_ZVE32F,		\
226 	RISCV_ISA_EXT_ZVE32X
227 
228 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
229 	RISCV_ISA_EXT_ZVE64F,		\
230 	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
231 
232 #define RISCV_ISA_EXT_V_IMPLY_LIST	\
233 	RISCV_ISA_EXT_ZVE64D,		\
234 	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
235 
236 static const unsigned int riscv_zve32f_exts[] = {
237 	RISCV_ISA_EXT_ZVE32X
238 };
239 
240 static const unsigned int riscv_zve64f_exts[] = {
241 	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
242 };
243 
244 static const unsigned int riscv_zve64d_exts[] = {
245 	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
246 };
247 
248 static const unsigned int riscv_v_exts[] = {
249 	RISCV_ISA_EXT_V_IMPLY_LIST
250 };
251 
252 static const unsigned int riscv_zve64x_exts[] = {
253 	RISCV_ISA_EXT_ZVE32X,
254 	RISCV_ISA_EXT_ZVE64X
255 };
256 
257 /*
258  * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
259  * privileged ISA, the existence of the CSRs is implied by any extension which
260  * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
261  * existence of the CSR, and treat it as a subset of those other extensions.
262  */
263 static const unsigned int riscv_xlinuxenvcfg_exts[] = {
264 	RISCV_ISA_EXT_XLINUXENVCFG
265 };
266 
267 /*
268  * Zc* spec states that:
269  * - C always implies Zca
270  * - C+F implies Zcf (RV32 only)
271  * - C+D implies Zcd
272  *
273  * These extensions will be enabled and then validated depending on the
274  * availability of F/D RV32.
275  */
276 static const unsigned int riscv_c_exts[] = {
277 	RISCV_ISA_EXT_ZCA,
278 	RISCV_ISA_EXT_ZCF,
279 	RISCV_ISA_EXT_ZCD,
280 };
281 
282 /*
283  * The canonical order of ISA extension names in the ISA string is defined in
284  * chapter 27 of the unprivileged specification.
285  *
286  * Ordinarily, for in-kernel data structures, this order is unimportant but
287  * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
288  *
289  * The specification uses vague wording, such as should, when it comes to
290  * ordering, so for our purposes the following rules apply:
291  *
292  * 1. All multi-letter extensions must be separated from other extensions by an
293  *    underscore.
294  *
295  * 2. Additional standard extensions (starting with 'Z') must be sorted after
296  *    single-letter extensions and before any higher-privileged extensions.
297  *
298  * 3. The first letter following the 'Z' conventionally indicates the most
299  *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
300  *    If multiple 'Z' extensions are named, they must be ordered first by
301  *    category, then alphabetically within a category.
302  *
303  * 3. Standard supervisor-level extensions (starting with 'S') must be listed
304  *    after standard unprivileged extensions.  If multiple supervisor-level
305  *    extensions are listed, they must be ordered alphabetically.
306  *
307  * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
308  *    after any lower-privileged, standard extensions.  If multiple
309  *    machine-level extensions are listed, they must be ordered
310  *    alphabetically.
311  *
312  * 5. Non-standard extensions (starting with 'X') must be listed after all
313  *    standard extensions. If multiple non-standard extensions are listed, they
314  *    must be ordered alphabetically.
315  *
316  * An example string following the order is:
317  *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
318  *
319  * New entries to this struct should follow the ordering rules described above.
320  */
321 const struct riscv_isa_ext_data riscv_isa_ext[] = {
322 	__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
323 	__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
324 	__RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
325 	__RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
326 	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
327 	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
328 	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
329 	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
330 	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
331 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
332 					  riscv_ext_zicbom_validate),
333 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
334 					  riscv_ext_zicboz_validate),
335 	__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
336 	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
337 	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
338 	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
339 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
340 	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
341 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
342 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
343 	__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
344 	__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
345 	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
346 	__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
347 	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
348 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
349 	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
350 	__RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
351 	__RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
352 	__RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
353 	__RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
354 	__RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
355 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
356 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
357 	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
358 	__RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
359 	__RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
360 	__RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
361 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
362 	__RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
363 	__RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
364 	__RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
365 	__RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
366 	__RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
367 	__RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
368 	__RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
369 	__RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
370 	__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
371 	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
372 	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
373 	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
374 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
375 	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
376 	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
377 	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
378 	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
379 	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
380 	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
381 	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
382 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
383 	__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
384 	__RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
385 	__RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
386 	__RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
387 	__RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
388 	__RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
389 	__RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
390 	__RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
391 	__RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
392 	__RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
393 	__RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
394 	__RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
395 	__RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
396 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
397 	__RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
398 	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
399 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
400 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
401 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
402 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
403 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
404 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
405 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
406 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
407 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
408 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
409 	__RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
410 };
411 
412 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
413 
riscv_isa_set_ext(const struct riscv_isa_ext_data * ext,unsigned long * bitmap)414 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
415 {
416 	if (ext->id != RISCV_ISA_EXT_INVALID)
417 		set_bit(ext->id, bitmap);
418 
419 	for (int i = 0; i < ext->subset_ext_size; i++) {
420 		if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
421 			set_bit(ext->subset_ext_ids[i], bitmap);
422 	}
423 }
424 
riscv_get_isa_ext_data(unsigned int ext_id)425 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id)
426 {
427 	for (int i = 0; i < riscv_isa_ext_count; i++) {
428 		if (riscv_isa_ext[i].id == ext_id)
429 			return &riscv_isa_ext[i];
430 	}
431 
432 	return NULL;
433 }
434 
435 /*
436  * "Resolve" a source ISA bitmap into one that matches kernel configuration as
437  * well as correct extension dependencies. Some extensions depends on specific
438  * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance)
439  * and this function will actually validate all the extensions provided in
440  * source_isa into the resolved_isa based on extensions validate() callbacks.
441  */
riscv_resolve_isa(unsigned long * source_isa,unsigned long * resolved_isa,unsigned long * this_hwcap,unsigned long * isa2hwcap)442 static void __init riscv_resolve_isa(unsigned long *source_isa,
443 				     unsigned long *resolved_isa, unsigned long *this_hwcap,
444 				     unsigned long *isa2hwcap)
445 {
446 	bool loop;
447 	const struct riscv_isa_ext_data *ext;
448 	DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX);
449 	int max_loop_count = riscv_isa_ext_count, ret;
450 	unsigned int bit;
451 
452 	do {
453 		loop = false;
454 		if (max_loop_count-- < 0) {
455 			pr_err("Failed to reach a stable ISA state\n");
456 			return;
457 		}
458 		bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX);
459 		for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) {
460 			ext = riscv_get_isa_ext_data(bit);
461 
462 			if (ext && ext->validate) {
463 				ret = ext->validate(ext, resolved_isa);
464 				if (ret == -EPROBE_DEFER) {
465 					loop = true;
466 					continue;
467 				} else if (ret) {
468 					/* Disable the extension entirely */
469 					clear_bit(bit, source_isa);
470 					continue;
471 				}
472 			}
473 
474 			set_bit(bit, resolved_isa);
475 			/* No need to keep it in source isa now that it is enabled */
476 			clear_bit(bit, source_isa);
477 
478 			/* Single letter extensions get set in hwcap */
479 			if (bit < RISCV_ISA_EXT_BASE)
480 				*this_hwcap |= isa2hwcap[bit];
481 		}
482 	} while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
483 }
484 
match_isa_ext(const char * name,const char * name_end,unsigned long * bitmap)485 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
486 {
487 	for (int i = 0; i < riscv_isa_ext_count; i++) {
488 		const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
489 
490 		if ((name_end - name == strlen(ext->name)) &&
491 		    !strncasecmp(name, ext->name, name_end - name)) {
492 			riscv_isa_set_ext(ext, bitmap);
493 			break;
494 		}
495 	}
496 }
497 
riscv_parse_isa_string(const char * isa,unsigned long * bitmap)498 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap)
499 {
500 	/*
501 	 * For all possible cpus, we have already validated in
502 	 * the boot process that they at least contain "rv" and
503 	 * whichever of "32"/"64" this kernel supports, and so this
504 	 * section can be skipped.
505 	 */
506 	isa += 4;
507 
508 	while (*isa) {
509 		const char *ext = isa++;
510 		const char *ext_end = isa;
511 		bool ext_err = false;
512 
513 		switch (*ext) {
514 		case 'x':
515 		case 'X':
516 			if (acpi_disabled)
517 				pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
518 			/*
519 			 * To skip an extension, we find its end.
520 			 * As multi-letter extensions must be split from other multi-letter
521 			 * extensions with an "_", the end of a multi-letter extension will
522 			 * either be the null character or the "_" at the start of the next
523 			 * multi-letter extension.
524 			 */
525 			for (; *isa && *isa != '_'; ++isa)
526 				;
527 			ext_err = true;
528 			break;
529 		case 's':
530 			/*
531 			 * Workaround for invalid single-letter 's' & 'u' (QEMU).
532 			 * No need to set the bit in riscv_isa as 's' & 'u' are
533 			 * not valid ISA extensions. It works unless the first
534 			 * multi-letter extension in the ISA string begins with
535 			 * "Su" and is not prefixed with an underscore.
536 			 */
537 			if (ext[-1] != '_' && ext[1] == 'u') {
538 				++isa;
539 				ext_err = true;
540 				break;
541 			}
542 			fallthrough;
543 		case 'S':
544 		case 'z':
545 		case 'Z':
546 			/*
547 			 * Before attempting to parse the extension itself, we find its end.
548 			 * As multi-letter extensions must be split from other multi-letter
549 			 * extensions with an "_", the end of a multi-letter extension will
550 			 * either be the null character or the "_" at the start of the next
551 			 * multi-letter extension.
552 			 *
553 			 * Next, as the extensions version is currently ignored, we
554 			 * eliminate that portion. This is done by parsing backwards from
555 			 * the end of the extension, removing any numbers. This may be a
556 			 * major or minor number however, so the process is repeated if a
557 			 * minor number was found.
558 			 *
559 			 * ext_end is intended to represent the first character *after* the
560 			 * name portion of an extension, but will be decremented to the last
561 			 * character itself while eliminating the extensions version number.
562 			 * A simple re-increment solves this problem.
563 			 */
564 			for (; *isa && *isa != '_'; ++isa)
565 				if (unlikely(!isalnum(*isa)))
566 					ext_err = true;
567 
568 			ext_end = isa;
569 			if (unlikely(ext_err))
570 				break;
571 
572 			if (!isdigit(ext_end[-1]))
573 				break;
574 
575 			while (isdigit(*--ext_end))
576 				;
577 
578 			if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
579 				++ext_end;
580 				break;
581 			}
582 
583 			while (isdigit(*--ext_end))
584 				;
585 
586 			++ext_end;
587 			break;
588 		default:
589 			/*
590 			 * Things are a little easier for single-letter extensions, as they
591 			 * are parsed forwards.
592 			 *
593 			 * After checking that our starting position is valid, we need to
594 			 * ensure that, when isa was incremented at the start of the loop,
595 			 * that it arrived at the start of the next extension.
596 			 *
597 			 * If we are already on a non-digit, there is nothing to do. Either
598 			 * we have a multi-letter extension's _, or the start of an
599 			 * extension.
600 			 *
601 			 * Otherwise we have found the current extension's major version
602 			 * number. Parse past it, and a subsequent p/minor version number
603 			 * if present. The `p` extension must not appear immediately after
604 			 * a number, so there is no fear of missing it.
605 			 *
606 			 */
607 			if (unlikely(!isalpha(*ext))) {
608 				ext_err = true;
609 				break;
610 			}
611 
612 			if (!isdigit(*isa))
613 				break;
614 
615 			while (isdigit(*++isa))
616 				;
617 
618 			if (tolower(*isa) != 'p')
619 				break;
620 
621 			if (!isdigit(*++isa)) {
622 				--isa;
623 				break;
624 			}
625 
626 			while (isdigit(*++isa))
627 				;
628 
629 			break;
630 		}
631 
632 		/*
633 		 * The parser expects that at the start of an iteration isa points to the
634 		 * first character of the next extension. As we stop parsing an extension
635 		 * on meeting a non-alphanumeric character, an extra increment is needed
636 		 * where the succeeding extension is a multi-letter prefixed with an "_".
637 		 */
638 		if (*isa == '_')
639 			++isa;
640 
641 		if (unlikely(ext_err))
642 			continue;
643 
644 		match_isa_ext(ext, ext_end, bitmap);
645 	}
646 }
647 
riscv_fill_hwcap_from_isa_string(unsigned long * isa2hwcap)648 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
649 {
650 	struct device_node *node;
651 	const char *isa;
652 	int rc;
653 	struct acpi_table_header *rhct;
654 	acpi_status status;
655 	unsigned int cpu;
656 	u64 boot_vendorid;
657 	u64 boot_archid;
658 
659 	if (!acpi_disabled) {
660 		status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
661 		if (ACPI_FAILURE(status))
662 			return;
663 	}
664 
665 	boot_vendorid = riscv_get_mvendorid();
666 	boot_archid = riscv_get_marchid();
667 
668 	for_each_possible_cpu(cpu) {
669 		struct riscv_isainfo *isainfo = &hart_isa[cpu];
670 		unsigned long this_hwcap = 0;
671 		DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
672 
673 		if (acpi_disabled) {
674 			node = of_cpu_device_node_get(cpu);
675 			if (!node) {
676 				pr_warn("Unable to find cpu node\n");
677 				continue;
678 			}
679 
680 			rc = of_property_read_string(node, "riscv,isa", &isa);
681 			of_node_put(node);
682 			if (rc) {
683 				pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
684 				continue;
685 			}
686 		} else {
687 			rc = acpi_get_riscv_isa(rhct, cpu, &isa);
688 			if (rc < 0) {
689 				pr_warn("Unable to get ISA for the hart - %d\n", cpu);
690 				continue;
691 			}
692 		}
693 
694 		riscv_parse_isa_string(isa, source_isa);
695 
696 		/*
697 		 * These ones were as they were part of the base ISA when the
698 		 * port & dt-bindings were upstreamed, and so can be set
699 		 * unconditionally where `i` is in riscv,isa on DT systems.
700 		 */
701 		if (acpi_disabled) {
702 			set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
703 			set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
704 			set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
705 			set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
706 		}
707 
708 		/*
709 		 * "V" in ISA strings is ambiguous in practice: it should mean
710 		 * just the standard V-1.0 but vendors aren't well behaved.
711 		 * Many vendors with T-Head CPU cores which implement the 0.7.1
712 		 * version of the vector specification put "v" into their DTs.
713 		 * CPU cores with the ratified spec will contain non-zero
714 		 * marchid.
715 		 */
716 		if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
717 			this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
718 			clear_bit(RISCV_ISA_EXT_v, source_isa);
719 		}
720 
721 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
722 
723 		/*
724 		 * All "okay" hart should have same isa. Set HWCAP based on
725 		 * common capabilities of every "okay" hart, in case they don't
726 		 * have.
727 		 */
728 		if (elf_hwcap)
729 			elf_hwcap &= this_hwcap;
730 		else
731 			elf_hwcap = this_hwcap;
732 
733 		if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
734 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
735 		else
736 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
737 	}
738 
739 	if (!acpi_disabled && rhct)
740 		acpi_put_table((struct acpi_table_header *)rhct);
741 }
742 
riscv_fill_cpu_vendor_ext(struct device_node * cpu_node,int cpu)743 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu)
744 {
745 	if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
746 		return;
747 
748 	for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
749 		struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
750 
751 		for (int j = 0; j < ext_list->ext_data_count; j++) {
752 			const struct riscv_isa_ext_data ext = ext_list->ext_data[j];
753 			struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];
754 
755 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",
756 						     ext.property) < 0)
757 				continue;
758 
759 			/*
760 			 * Assume that subset extensions are all members of the
761 			 * same vendor.
762 			 */
763 			if (ext.subset_ext_size)
764 				for (int k = 0; k < ext.subset_ext_size; k++)
765 					set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
766 
767 			set_bit(ext.id, isavendorinfo->isa);
768 		}
769 	}
770 }
771 
772 /*
773  * Populate all_harts_isa_bitmap for each vendor with all of the extensions that
774  * are shared across CPUs for that vendor.
775  */
riscv_fill_vendor_ext_list(int cpu)776 static void __init riscv_fill_vendor_ext_list(int cpu)
777 {
778 	if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
779 		return;
780 
781 	for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
782 		struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
783 
784 		if (!ext_list->is_initialized) {
785 			bitmap_copy(ext_list->all_harts_isa_bitmap.isa,
786 				    ext_list->per_hart_isa_bitmap[cpu].isa,
787 				    RISCV_ISA_VENDOR_EXT_MAX);
788 			ext_list->is_initialized = true;
789 		} else {
790 			bitmap_and(ext_list->all_harts_isa_bitmap.isa,
791 				   ext_list->all_harts_isa_bitmap.isa,
792 				   ext_list->per_hart_isa_bitmap[cpu].isa,
793 				   RISCV_ISA_VENDOR_EXT_MAX);
794 		}
795 	}
796 }
797 
has_thead_homogeneous_vlenb(void)798 static int has_thead_homogeneous_vlenb(void)
799 {
800 	int cpu;
801 	u32 prev_vlenb = 0;
802 	u32 vlenb;
803 
804 	/* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */
805 	if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR))
806 		return 0;
807 
808 	for_each_possible_cpu(cpu) {
809 		struct device_node *cpu_node;
810 
811 		cpu_node = of_cpu_device_node_get(cpu);
812 		if (!cpu_node) {
813 			pr_warn("Unable to find cpu node\n");
814 			return -ENOENT;
815 		}
816 
817 		if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) {
818 			of_node_put(cpu_node);
819 
820 			if (prev_vlenb)
821 				return -ENOENT;
822 			continue;
823 		}
824 
825 		if (prev_vlenb && vlenb != prev_vlenb) {
826 			of_node_put(cpu_node);
827 			return -ENOENT;
828 		}
829 
830 		prev_vlenb = vlenb;
831 		of_node_put(cpu_node);
832 	}
833 
834 	thead_vlenb_of = vlenb;
835 	return 0;
836 }
837 
riscv_fill_hwcap_from_ext_list(unsigned long * isa2hwcap)838 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
839 {
840 	unsigned int cpu;
841 	bool mitigated;
842 
843 	for_each_possible_cpu(cpu) {
844 		unsigned long this_hwcap = 0;
845 		struct device_node *cpu_node;
846 		struct riscv_isainfo *isainfo = &hart_isa[cpu];
847 		DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
848 
849 		cpu_node = of_cpu_device_node_get(cpu);
850 		if (!cpu_node) {
851 			pr_warn("Unable to find cpu node\n");
852 			continue;
853 		}
854 
855 		if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
856 			of_node_put(cpu_node);
857 			continue;
858 		}
859 
860 		for (int i = 0; i < riscv_isa_ext_count; i++) {
861 			const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
862 
863 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",
864 						     ext->property) < 0)
865 				continue;
866 
867 			riscv_isa_set_ext(ext, source_isa);
868 		}
869 
870 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
871 		riscv_fill_cpu_vendor_ext(cpu_node, cpu);
872 
873 		of_node_put(cpu_node);
874 
875 		/*
876 		 * All "okay" harts should have same isa. Set HWCAP based on
877 		 * common capabilities of every "okay" hart, in case they don't.
878 		 */
879 		if (elf_hwcap)
880 			elf_hwcap &= this_hwcap;
881 		else
882 			elf_hwcap = this_hwcap;
883 
884 		if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
885 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
886 		else
887 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
888 
889 		riscv_fill_vendor_ext_list(cpu);
890 	}
891 
892 	/*
893 	 * Execute ghostwrite mitigation immediately after detecting extensions
894 	 * to disable xtheadvector if necessary.
895 	 */
896 	mitigated = ghostwrite_enable_mitigation();
897 
898 	if (!mitigated && has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() < 0) {
899 		pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n");
900 		disable_xtheadvector();
901 	}
902 
903 	if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
904 		return -ENOENT;
905 
906 	return 0;
907 }
908 
909 #ifdef CONFIG_RISCV_ISA_FALLBACK
910 bool __initdata riscv_isa_fallback = true;
911 #else
912 bool __initdata riscv_isa_fallback;
riscv_isa_fallback_setup(char * __unused)913 static int __init riscv_isa_fallback_setup(char *__unused)
914 {
915 	riscv_isa_fallback = true;
916 	return 1;
917 }
918 early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
919 #endif
920 
riscv_fill_hwcap(void)921 void __init riscv_fill_hwcap(void)
922 {
923 	char print_str[NUM_ALPHA_EXTS + 1];
924 	unsigned long isa2hwcap[26] = {0};
925 	int i, j;
926 
927 	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
928 	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
929 	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
930 	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
931 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
932 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
933 	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
934 
935 	if (!acpi_disabled) {
936 		riscv_fill_hwcap_from_isa_string(isa2hwcap);
937 	} else {
938 		int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
939 
940 		if (ret && riscv_isa_fallback) {
941 			pr_info("Falling back to deprecated \"riscv,isa\"\n");
942 			riscv_fill_hwcap_from_isa_string(isa2hwcap);
943 		}
944 	}
945 
946 	/*
947 	 * We don't support systems with F but without D, so mask those out
948 	 * here.
949 	 */
950 	if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
951 		pr_info("This kernel does not support systems with F but not D\n");
952 		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
953 	}
954 
955 	if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) ||
956 	    has_xtheadvector_no_alternatives()) {
957 		/*
958 		 * This cannot fail when called on the boot hart
959 		 */
960 		riscv_v_setup_vsize();
961 	}
962 
963 	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
964 		/*
965 		 * ISA string in device tree might have 'v' flag, but
966 		 * CONFIG_RISCV_ISA_V is disabled in kernel.
967 		 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
968 		 */
969 		if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
970 			elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
971 	}
972 
973 	memset(print_str, 0, sizeof(print_str));
974 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
975 		if (riscv_isa[0] & BIT_MASK(i))
976 			print_str[j++] = (char)('a' + i);
977 	pr_info("riscv: base ISA extensions %s\n", print_str);
978 
979 	memset(print_str, 0, sizeof(print_str));
980 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
981 		if (elf_hwcap & BIT_MASK(i))
982 			print_str[j++] = (char)('a' + i);
983 	pr_info("riscv: ELF capabilities %s\n", print_str);
984 }
985 
riscv_get_elf_hwcap(void)986 unsigned long riscv_get_elf_hwcap(void)
987 {
988 	unsigned long hwcap;
989 
990 	hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
991 
992 	if (!riscv_v_vstate_ctrl_user_allowed())
993 		hwcap &= ~COMPAT_HWCAP_ISA_V;
994 
995 	return hwcap;
996 }
997 
riscv_user_isa_enable(void)998 void __init riscv_user_isa_enable(void)
999 {
1000 	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
1001 		current->thread.envcfg |= ENVCFG_CBZE;
1002 	else if (any_cpu_has_zicboz)
1003 		pr_warn("Zicboz disabled as it is unavailable on some harts\n");
1004 }
1005 
1006 #ifdef CONFIG_RISCV_ALTERNATIVE
1007 /*
1008  * Alternative patch sites consider 48 bits when determining when to patch
1009  * the old instruction sequence with the new. These bits are broken into a
1010  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1011  * patch site is for an erratum, identified by the 32-bit patch ID. When
1012  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
1013  * further break down patch ID into two 16-bit numbers. The lower 16 bits
1014  * are the cpufeature ID and the upper 16 bits are used for a value specific
1015  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
1016  * implies no specific value is specified. cpufeatures that want to control
1017  * patching on a per-site basis will provide non-zero values and implement
1018  * checks here. The checks return true when patching should be done, and
1019  * false otherwise.
1020  */
riscv_cpufeature_patch_check(u16 id,u16 value)1021 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
1022 {
1023 	if (!value)
1024 		return true;
1025 
1026 	switch (id) {
1027 	case RISCV_ISA_EXT_ZICBOZ:
1028 		/*
1029 		 * Zicboz alternative applications provide the maximum
1030 		 * supported block size order, or zero when it doesn't
1031 		 * matter. If the current block size exceeds the maximum,
1032 		 * then the alternative cannot be applied.
1033 		 */
1034 		return riscv_cboz_block_size <= (1U << value);
1035 	}
1036 
1037 	return false;
1038 }
1039 
riscv_cpufeature_patch_func(struct alt_entry * begin,struct alt_entry * end,unsigned int stage)1040 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
1041 						  struct alt_entry *end,
1042 						  unsigned int stage)
1043 {
1044 	struct alt_entry *alt;
1045 	void *oldptr, *altptr;
1046 	u16 id, value, vendor;
1047 
1048 	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
1049 		return;
1050 
1051 	for (alt = begin; alt < end; alt++) {
1052 		id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
1053 		vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
1054 
1055 		/*
1056 		 * Any alternative with a patch_id that is less than
1057 		 * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
1058 		 *
1059 		 * Any alternative with patch_id that is greater than or equal
1060 		 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
1061 		 * vendor extension.
1062 		 */
1063 		if (id < RISCV_ISA_EXT_MAX) {
1064 			/*
1065 			 * This patch should be treated as errata so skip
1066 			 * processing here.
1067 			 */
1068 			if (alt->vendor_id != 0)
1069 				continue;
1070 
1071 			if (!__riscv_isa_extension_available(NULL, id))
1072 				continue;
1073 
1074 			value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
1075 			if (!riscv_cpufeature_patch_check(id, value))
1076 				continue;
1077 		} else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
1078 			if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor,
1079 								    id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))
1080 				continue;
1081 		} else {
1082 			WARN(1, "This extension id:%d is not in ISA extension list", id);
1083 			continue;
1084 		}
1085 
1086 		oldptr = ALT_OLD_PTR(alt);
1087 		altptr = ALT_ALT_PTR(alt);
1088 
1089 		mutex_lock(&text_mutex);
1090 		patch_text_nosync(oldptr, altptr, alt->alt_len);
1091 		riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
1092 		mutex_unlock(&text_mutex);
1093 	}
1094 }
1095 #endif
1096